S1K70000 Datasheet, PDF (33/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 2 Estimating the Gate Density
Chapter 2 Estimating the Gate Density
This chapter describes the procedure for estimating the circuit size after cutting out
circuits from the customer’s system, and then estimating an approximate bulk size.
The precautions to be taken when performing this work are also described.
2.1 Dividing Up Logic Between Chips
When cutting out circuits from the customer’s system, care must be taken with respect to
the following points.
• Precautions to be taken
(1) Logic size to be integrated (Gate count)
(2) Number of I/O pins required (Pin count)
(3) Package to be used
(4) Power consumption
Generally speaking, as the circuit size increases, so does the power consumption of the
circuit and the number of input/output pins on it. If the circuit size is significantly large,
the circuit may be divided into multiple chips rather than being integrated into a single
chip. This helps reduce the total cost and the power consumption of the circuit.
STANDARD CELL S1K70000 SERIES
EPSON
25
EMBEDDED ARRAY S1X70000 SERIES