S1D13705F00A200 Datasheet, PDF (89/562 Pages) EPCOS – Embedded Memory LCD Controller

Epson Research and Development
Vancouver Design Center
Page 83
13.3 Power Save Mode Function Summary
Table 13-4: Power Save Mode Function Summary
IO Access Possible?
Memory Access Possible?
Look-Up Table Registers Access Possible?
Sequence Controller Running?
Display Active?
LCDPWR
FPDAT[11:0], FPSHIFT (see note)
FPLINE, FPFRAME, DRDY
Hardware
Power Save
No
No
No
No
No
Inactive
Forced Low
Forced Low
Software
Power Save
Yes
Yes
No
No
No
Inactive
Forced Low
Forced Low
Normal
Yes
Yes
Yes
Yes
Yes
Active
Active
Active
Note
When FPDAT[11:8] are designated as GPIO outputs, the output state prior to enabling
the Power Save Mode is maintained. When FPDAT[11:8] are designated as GPIO in-
puts, unused inputs must be tied to either IO V_DD or GND - see Table 5.5 “LCD Inter-
face Pin Mapping,” on page 23.
13.4 Panel Power Up/Down Sequence
After chip reset or when entering/exiting a power save mode, the Panel Interface signals
follow a power on/off sequence shown below. This sequence is essential to prevent damage
to the LCD panel.
Hardware Functional Specification
Issue Date: 02/02/01
S1D13705
X27A-A-001-10