S1D13705F00A200 Datasheet, PDF (407/562 Pages) EPCOS – Embedded Memory LCD Controller

Epson Research and Development
Vancouver Design Center
Page 21
Width) set to 1 for a 16-bit bus, and the WS (Wait states) bit should be set to 111b to allow
the S1D13705 to terminate bus cycles externally with DTACK. Enable DTACK pin
function with Register FFFFF433, Port G Select Register, bit 0.
Interfacing to the Motorola ‘Dragonball’ Family of Microprocessors
Issue Date: 01/02/13
S1D13705
X27A-G-007-04