S1D13705F00A200 Datasheet, PDF (40/562 Pages) EPCOS – Embedded Memory LCD Controller

Page 34
Epson Research and Development
Vancouver Design Center
7.2 Clock Input Requirements
Clock Input Waveform
90%
VIH
VIL
10%
tr
tPWH
tPWL
tf
TCLKI
Figure 7-7: Clock Input Requirements for CLKI
Symbol
f_CLKI
T_CLKI
t_PWH
t_PWL
t_f
t_r
Table 7-7: Clock Input Requirements for CLKI
Parameter
Input Clock Frequency (CLKI)
Min
Max
50
Input Clock period (CLKI)
Input Clock Pulse Width High (CLKI)
Input Clock Pulse Width Low (CLKI)
1/f_CLKI
8
8
Input Clock Fall Time (10% - 90%)
5
Input Clock Rise Time (10% - 90%)
5
Units
MHz
ns
ns
ns
ns
ns
Note
When CLKI is > 25MHz the Input Clock Divide bit (REG[02h] bit 4) must be set to 1.
S1D13705
X27A-A-001-10
Hardware Functional Specification
Issue Date: 02/02/01