S1D13705F00A200 Datasheet, PDF (36/562 Pages) EPCOS – Embedded Memory LCD Controller

Page 30
Epson Research and Development
Vancouver Design Center
7.1.3 Motorola MC68K #1 Interface Timing
CLK
T_CLK
A[16:1]
CS#
R/W#
VALID
t1
t2
AS#
UDS#, LDS#
DTACK#
D[15:0]
(write
D[15:0]
(read)
INVALID
t3
Hi-Z
Hi-Z
Hi-Z
t4
t8
t10
t11
t5
VALID
VALID
t7
t6
t9
t12
Figure 7-3: MC68K #1 Bus Timing (MC68000)
Hi-Z
Hi-Z
Hi-Z
Symbol
f_CLK
T_CLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
Table 7-3: MC68K #1 Bus Timing (MC68000)
Parameter
Bus Clock Frequency
Bus Clock period
A[16:1], CS# valid before AS# falling edge
A[16:1], CS# hold from AS# rising edge
AS# low to DTACK# driven high
CLK to DTACK# low
CLK to AS#, UDS#, LDS# high
AS# high to DTACK# high
AS# high to DTACK# high impedance
UDS#, LDS# falling edge to D[15:0] valid (write cycle)
D[15:0] hold from AS# rising edge (write cycle)
UDS#, LDS# falling edge to D[15:0] driven (read cycle)
D[15:0] valid to DTACK# falling edge (read cycle)
UDS#, LDS# rising edge to D[15:0] high impedance
Min
1/f_CLK
0
0
1T_CLK
0
0
Max
33
16
15
20
T_CLK
T_CLK
15
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
CLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 84
S1D13705
X27A-A-001-10
Hardware Functional Specification
Issue Date: 02/02/01