S1D13705F00A200 Datasheet, PDF (38/562 Pages) EPCOS – Embedded Memory LCD Controller

Page 32
7.1.5 Generic #1 Interface Timing
T_BCLK
BCLK
A[16:0]
VALID
Epson Research and Development
Vancouver Design Center
CS#
t1
t2
WE0#,WE1#
RD0#, RD1#
t3
D[15:0]
Hi-Z
(write)
t4
D[15:0]
Hi-Z
(read)
t8
WAIT#
Hi-Z
VALID
t6
t9
VALID
t11
t5
t7
Hi-Z
t10
Hi-Z
Figure 7-5: Generic #1 Timing
Table 7-5: Generic #1 Timing
Symbol
f_BCLK
T_BCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Parameter
Bus Clock frequency
Bus Clock period
A[16:0], CS# valid to WE0#, WE1# low (write cycle) or RD0#, RD1#
low (read cycle)
WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycle) to
A[16:0], CS# invalid
WE0#, WE1# low to D[15:0] valid (write cycle)
RD0#, RD1# low to D[15:0] driven (read cycle)
WE0#, WE1# high to D[15:0] invalid (write cycle)
D[15:0] valid to WAIT# high (read cycle)
RD0#, RD1# high to D[15:0] high impedance (read cycle)
WE0#, WE1# low (write cycle) or RD0#, RD1# low (read cycle) to
WAIT# driven low
BCLK to WAIT# high
WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycle) to
WAIT# high impedance
WAIT# high to WE0#, WE1#, RD0#, RD1# high
Min
1/f_BCLK
0
0
0
0
1T_BCLK
Max
50
T_BCLK
17
10
16
16
16
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
BCLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 84
S1D13705
X27A-A-001-10
Hardware Functional Specification
Issue Date: 02/02/01