S1D13705F00A200 Datasheet, PDF (431/562 Pages) EPCOS – Embedded Memory LCD Controller

Epson Research and Development
Vancouver Design Center
Page 13
4.2 S1D13705 Hardware Configuration
The S1D13705 uses CNF3 through CNF0 and BS# to allow selection of the bus mode and
other configuration data on the rising edge of RESET#. Refer to the S1D13705 Hardware
Functional Specification, document number X27A-A-001-xx for details.
The tables below show those configuration settings important to the Generic #2 host bus
interface.
Table 4-1: Summary of Power-On/Reset Options
Signal
CNF0
CNF1
CNF2
CNF3
value on this pin at the rising edge of RESET# is used to configure: (0/1)
0
1
See “Host Bus Selection” table below See “Host Bus Selection” table below
Little Endian
Big Endian
= configuration for NEC VR4102/VR4111 support
CNF2
1
Table 4-2: Host Bus Selection
CNF1
1
CNF0
1
BS#
Host Bus Interface
1
Generic #2, 16-bit
= configuration for NEC VR4102/VR4111 support
Interfacing to the NEC VR4102/VR4111 Microprocessor
Issue Date: 01/02/13
S1D13705
X27A-G-008-02