S1D13705F00A200 Datasheet, PDF (372/562 Pages) EPCOS – Embedded Memory LCD Controller

Page 12
Epson Research and Development
Vancouver Design Center
4 Direct Connection to the Toshiba TMPR3912
4.1 General Description
In this example implementation, the S1D13705 occupies the TMPR3912 PC Card slot #1.
The S1D13705 is easily interfaced to the TMPR3912 with minimal additional logic. The
address bus of the TMPR3912 PC Card interface is multiplexed and must be demultiplexed
using an advanced CMOS latch (e.g., 74AHC373). The direct connection approach makes
use of the S1D13705 in its “Generic Interface #2” configuration.
The following diagram demonstrates a typical implementation of the interface.
TMPR3912
CARDIORD*
CARDIOWR*
CARD1CSL*
CARD1CSH*
ENDIAN
ALE
A[12:0]
D[31:24]
D[23:16]
CARD1WAIT*
DCLKOUT
Latch
V_{DD pull-up}
Clock divider
+3.3V
S1D13705
IO V_DD, CORE V_DD
RD#
WE0#
+3.3V
+3.3V
System RESET
WE1#
BS#
RD/WR#
RESET#
CS#
AB[16:13]
AB[12:0]
DB[7:0]
DB[15:8]
...or...
Oscillator
See text
WAIT#
CLKI
BCLK
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: S1D13705 to TMPR3912 Direct Connection
Note
See Section 3.1 on page 9 and Section 3.3 on page 11 for Generic #2 pin descriptions.
S1D13705
X27A-G-004-02
Interfacing to the Toshiba MIPS TMPR3912 Microprocessor
Issue Date: 01/02/13