S1D13705F00A200 Datasheet, PDF (536/562 Pages) EPCOS – Embedded Memory LCD Controller

Page 8
2 Interfacing to the NEC VR4181A
Epson Research and Development
Vancouver Design Center
2.1 The NEC VR4181A System Bus
The VR-Series family of microprocessors features a high-speed synchronous system bus
typical of modern microprocessors. Designed with external LCD controller support and
Windows CE based embedded consumer applications in mind, the VR4181A offers a
highly integrated solution for portable systems. This section is an overview of the operation
of the CPU bus to establish interface requirements.
2.1.1 Overview
The NEC VR4181A is designed around the RISC architecture developed by MIPS. This
microprocessor is designed around the 100MHz VR4110 CPU core which supports the
MIPS III and MIPS16 instruction sets. The CPU communicates with external devices via
an ISA interface.
The NEC VR4181A has direct support for an external LCD controller. A 64 to 512-kilobyte
block of memory is assigned to the LCD controller with a dedicated chip select signal.
Word or byte accesses are controlled by the system high byte signal, #UBE.
S1D13705
X27A-G-013-02
Interfacing to the NEC VR4181A™ Microprocessor
Issue Date: 01/02/13