S1D13705F00A200 Datasheet, PDF (557/562 Pages) EPCOS – Embedded Memory LCD Controller

Epson Research and Development
Vancouver Design Center
4 8-Bit Processor to S1D13705 Interface
Page 11
4.1 Hardware Description
The interface between the S1D13705 and an 8-bit processor requires minimal glue logic. A
decoder is used to generate the chip select for the S1D13705 based on where the S1D13705
is mapped into memory. Alternatively, if the processor supports a chip select module, it can
be programmed to generate a chip select for the S1D13705 without the need of an address
decoder.
An inverter inverts A0 to generate the Byte High Enable signal for the S1D13705. If the
8-bit host interface has an active high WAIT signal, it must be inverted as well.
In order to support an 8-bit microprocessor with a 16-bit peripheral, the low and high order
bytes of the data bus must be connected together. The following diagram shows a typical
implementation of an 8-bit processor interfaced to the S1D13705.
Generic 8-bit Bus
A[0]
A[16:1]
D[7:0]
WAIT#
WE#
RD#
BUSCLK
Decoder
S1D13705
AB[0]
AB[16:1]
DB[7:0]
DB[15:8]
CS#
IO V_DD
System RESET
WAIT#
WE0#
RD#
BHE# (WE1#)
RD/WR#
BS#
BUSCLK
RESET#
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of an 8-bit Processor to the S1D13705 Generic #2 Interface
Interfacing to an 8-bit Processor
Issue Date: 01/12/20
S1D13705
X27A-G-015-01