S1D13705F00A200 Datasheet, PDF (28/562 Pages) EPCOS – Embedded Memory LCD Controller

Page 22
5.3 Summary of Configuration Options
Epson Research and Development
Vancouver Design Center
Configuration
Pin
CNF[3:0]
Table 5-1: Summary of Power On/Reset Options
Power On/Reset State
Select host bus interface as follows:
CNF3 CNF2 CNF1 CNF0 BS#
1
0
0
0
X
0
0
0
0
X
1
0
0
1
X
0
0
0
1
X
X
0
1
0
X
1
0
1
1
X
0
0
1
1
X
X
1
0
0
X
1
1
0
1
X
0
1
0
1
X
X
1
1
0
0
X
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
Host Bus
SH-4 interface Big Endian
SH-4 interface Little Endian
SH-3 interface Big Endian
SH-3 interface Little Endian
reserved
MC68K #1, 16-bit Big Endian
reserved
reserved
MC68K #2, 16-bit Big Endian
reserved
reserved
reserved
Generic #1, 16-bit Big Endian
Generic #1, 16-bit Little Endian
reserved
Generic #2, 16-bit Little Endian
5.4 Host Bus Interface Pin Mapping
S1D13705
Pin Names
AB[16:1]
AB0
DB[15:0]
WE1#
CS#
BCLK
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
SH-3
A[16:1]
A0
D[15:0]
WE1#
CSn#
CKIO
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
Table 5-2: Host Bus Interface Pin Mapping
SH-4
MC68K #1
MC68K #2
Generic #1
Generic #2
A[16:1]
A0
D[15:0]
WE1#
CSn#
CKIO
BS#
RD/WR#
RD#
WE0#
RDY#
RESET#
A[16:1]
A[16:1]
A[16:1]
A[16:1]
LDS#
A0
A0
A0
D[15:0]
D[31:16]
D[15:0]
D[15:0]
UDS#
DS#
WE1#
BHE#
External Decode External Decode External Decode External Decode
CLK
CLK
BCLK
BCLK
AS#
R/W#
connect to IO V_DD
connect to IO V_DD
DTACK#
AS#
R/W#
SIZ1
SIZ0
DSACK1#
connect to V_SS connect to IO V_DD
RD1#
connect to IO V_DD
RD0#
RD#
WE0#
WE#
WAIT#
WAIT#
RESET#
RESET#
RESET#
RESET#
S1D13705
X27A-A-001-10
Hardware Functional Specification
Issue Date: 02/02/01