S1D13705F00A200 Datasheet, PDF (423/562 Pages) EPCOS – Embedded Memory LCD Controller

Epson Research and Development
Vancouver Design Center
List of Tables
Page 5
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4-2: Host Bus Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
List of Figures
Figure 2-1: NEC VR4102/VR4111 Read/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4-1: Typical Implementation of VR4102/VR4111 to S1D13705 Interface . . . . . . . . . . . 14
Interfacing to the NEC VR4102/VR4111 Microprocessor
Issue Date: 01/02/13
S1D13705
X27A-G-008-02