MA17502 Datasheet, PDF (6/30 Pages) Dynex Semiconductor – Radiation Hard MIL-STD-1750A Control Unit

MA17502
stores the processor state, retrieves the highest priority
pending interrupt’s service routine processor state, and vectors
software execution to the user’s interrupt service routine. IRN
originates in the IU.
3.4.2 Privileged Instruction Fault (PIFN)
A low on this signal causes the CU to enable control of the
DMA interface (located in the Interrupt Unit), abort the currently
executing MIL-STD-1750A instruction and check the IRN input
for a pending level 1 interrupt caused by the IU latching a
memory protect (MPROEN), memory address (EXADEN), or
Bus Time-out fault. PIFN originates in the IU.
3.4.3 Branch or Jump Control (T1)
Input. A high on this input directs the CU microcode address
sequencer to branch execution to a nonsequential microcode
address. This signal is under the control of the Execution Unit’s
ALU and its level is dependent on the outcome of the presently
executing microcode instruction, e.g. conditional branch. T1
originates in the EU.
3.5 CONFIGURATION CONTROL
The following inputs are provided for control of multiple CU
systems. They allow for expansion of the microcode store to 4K
40-bit words.
3.5.1 ROM-Only (ROMONLYN)
Input. This signal is provided for future microcode
expansion and must be pulled up to VDD.
3.5.2 Chip Select (CS)
Input. A high on this signal enables the CU to drive the 20-
bit external M Bus. This signal is provided for future microcode
expansion and must be pulled up to VDD.
3.6 CPU CONTROL
Grouped under this heading are signals that have CPU-
wide control of normal operation. Each of these has the ability
to “freeze” the processor.
3.6.1 Hold Request (HOLDN)
Input. A low on this input will suspend internal processor
functions at the end of the currently executing MlL-STD1750A
instruction. When this signal becomes active, the CU
completes the currently executing MIL-STD-1750A instruction,
then branches to the Hold microcode routine and enters the
Hold state. The CU will resume normal operation by refilling the
instruction pipeline registers (IA and IB) upon release of
HOLDN.
3.6.2 System Reset (RESET)
Input. A high on this input for a duration of at least one
CLKPCN period will reset the MAS281 chip set by forcing the
Control Unit to microcode address zero. The high-to-low
transition of this input will cause the CU to begin executing the
MAS281 initialisation sequence starting with the first instruction
in microcode. Built-in Test (BIT) is performed as part of the
initialisation sequence. At the conclusion of initialisation and
successful execution of BIT, the MAS281 will be initialised as
shown in Table 3.
4.0 OPERATING MODES
The following discussions detail the MAS281 chip set
operating modes from the perspective of the Control Unit.
MAS281 operating modes involving the MA17502 include: (1)
Initialisation, (2) lnstruction Execution, (3) Interrupt Servicing,
(4) DMA Support, and (5) HOLD Support.
4.1 INITIALISATION
The MA17502 sequences the MAS281 chip set through the
microcoded initialisation routine in response to a high pulse on
the RESET input. This routine clears the chip set registers,
disables and masks interrupts’ reads the configuration register,
resets the output discrete register (if applicable), initialises the
MMU and BPU (if applicable), performs Built-in Test (BIT),
raises the StartUp ROM Enable discrete, clears and starts
timers A and B, resets the Trigger-Go counter, and loads the
instruction pipeline. The initialisation sequence is contained in
the first 33 locations of microcode ROM (an additional 14
locations contain the optional MMU and BPU initialisation
code). Because the initialisation sequence clears the Execution
Unit’s lnstruction Counter and Status Word (also the address
and processor state copies stored in the MMU(BPU), if
applicable), program execution begins with the instruction
located at address zero (page zero). Table 2 provides a
detailed breakdown of the initialisation sequence and Table 3
summarises the resulting initialised state.
BIT occupies 332 words of microcode storage ROM, and
consists of five subroutines that exercise the internal circuitry of
the MAS281, as outlined in Table 4. BIT begins by pulling the
Normal Power-UP ((IU)NPU) output low; this is the first time
after power-up that the state of NPU is guaranteed. If all five
BIT subroutines execute successfully, NPU is raised high.
If any part of BIT fails, an error code identifying the failed
subroutine is loaded into the Interrupt Unit Fault Register (via
the AD Bus), BlT is aborted, and NPU is left in the low state.
Table 4 defines the coding of the BIT results. (NPU is raised
high through microcode control of the lU in conjunction with the
(EU)lNTREN signal. The BIT error codes are loaded in the lU
Fault Register via the AD Bus under microcode control of the lU
in conjunction with the (EU)lNTREN signal.)
ln the event of such a failure, the resulting chip set reset
state is dependent on where in BIT the error occurred and may
not be the same as that shown in Table 3. A BIT failure
indication in the fault register sets the level 1 pending interrupt.
Since initialisation disables and masks interrupts, the IRN input
will remain high; thus the interrupt will not be serviced
immediately.
The last action performed by the initialisation routine is to
load the instruction pipeline. lnstruction fetches start at memory
location zero (page zero) from the Start-Up ROM (if
implemented). Whether BlT passes or not, the processor will
begin instruction execution at this point.
Note: To complete initialisation and pass BIT, interrupt and
fault inputs must be high for the duration of the initialisation
routine. Also, the Timers A and B must be clocked for BIT
success.
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