MA17502 Datasheet, PDF (1/30 Pages) Dynex Semiconductor – Radiation Hard MIL-STD-1750A Control Unit

Replaces June 1999 version, DS3565-4.0
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Radiation Hard MIL-STD-1750A Control Unit
DS3565-5.0 January 2000
The MA17502 Control Unit is a component of the MAS281
chip set. Other chips in the set include the MA17501 Execution
Unit and the MA17503 Interrupt Unit. Also available is the
peripheral MA31751 Memory Management Unit/Block
Protection Unit. In conjunction these chips implement the full
MIL-STD-1750A Instruction Set Architecture.
The MA17502 consisting of a microsequencer, a microcode
storage ROM, and an instruction mapping ROM - controls all
chip set operations. Table 1 provides brief signal definitions.
The MA17502 is offered in several speed and screening
grades, and in dual in-line, flatpack or leadless chip carrier
packaging. Screening options are described in this document.
For availability of speed grades, please contact Dynex
Semiconductor.
FEATURES
s MIL-STD-1750A Instruction Set Architecture
s Full Performance Over Military Temperature Range
s 12-Bit Microsequencer
- Instruction Prefetch
- Pipelined Operation
- Subroutine Capability
s On-Chip ROM
- 2K x 40-Bit Microcode Store
- 512 x 8-Bit Instruction Map
s MAS281 Integrated Built-In Self Test
s TTL Compatible System Interface
s Low Power CMOS/SOS Technology
BLOCK DIAGRAM
1.0 SYSTEM CONSIDERATIONS
The MA17502 Control Unit (CU) is a component of the
Dynex Semiconductor MAS281 chip set. The other chips in the
set are the MA17501 Execution Unit (EU) and the MA17503
lnterrupt Unit (lU). Also available is the peripheral MA31751
Memory Management Unit/Block Protection Unit (MMU(BPU)).
The Control Unit, in conjunction with these chips, implements
the full MIL-STD-1750A lnstruction Set Architecture. Figure 1
depicts the relationship between the chip set components.
The CU provides the microprogram storage and
sequencing resources for the chip set. The EU provides the
MAS281’s system synchronizing and arithmetic/logic
computational resources. The lU provides interrupt and fault
handling resources, DMA interface control signals, and the
three MIL-STD-1750A timers. The MMU/BPU may be
configured to provide 1M-word memory management (MMU)
and/or 1K-word memory block write protection (BPU) functions.
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