MA17502 Datasheet, PDF (10/30 Pages) Dynex Semiconductor – Radiation Hard MIL-STD-1750A Control Unit

MA17502
5.2 ADDRESSING MODES
The MAS281 chip set supports the eight addressing
modes specified in MIL-STD-1750A. These addressing
modes are shown in Figure 5 and are defined below.
5.2.1 Register Direct (R)
The register specified by the instruction (RB) contains
the required operand.
5.2.2 Memory Direct (D,DX)
Memory Direct (without indexing) is an addressing
mode in which the instruction contains the memory address
(A) of the required operand. ln Memory Direct (indexed),
the memory address of the required operand is specified by
the sum of the contents of an index register (RX) and the
instruction address field (A). Registers R1 through R15
may be specified for indexing.
5.2.3 Memory Indirect (I,IX)
Memory Indirect (without indexing) is an addressing
mode in which the memory address (A) specified by the
instruction contains the address of the required operand. In
Memory Indirect (pre-indexed), the sum of the contents of a
specified index register (RX) and the instruction address
field (A) is the address of the address of the required
operand. Registers R1 through R15 may be specified for
indexing.
5.2.4 Immediate Long (IM)
There are two formats that implement Immediate Long
Addressing; one allows indexing and one does not. For the
indexable format, if the specified index register (RX) is not
equal to zero, the contents of RX are added to the
immediate field to form the required operand, otherwise,
the immediate field contains the required operand .
5.2.5 Immediate Short (IS)
In this mode the required 4-bit operand is contained
within the 16-bit instruction. The Immediate Short
addressing mode accommodates two formats; one which
interprets the contents of the immediate field as positive
data and the other which interprets the contents of the
immediate field as negative data.
5.2.6 Immediate Short Positive (ISP)
The immediate operand is treated as a positive integer
between 1 and 16.
Figure 4: Data Formats
5.2.7 Immediate Short Negative (ISN)
The immediate operand is treated as a negative integer
between 1 and 16. Its internal form is a two’s complement,
sign-extended 16-bit number.
5.2.8 Instruction Counter Relative (ICR)
This addressing mode is used for 16-bit branch
instructions. The contents of the instruction counter minus
two (the address of the current instruction) is added to the
sign-extended 8-bit displacement field (D) within the
instruction. This sum then points to the memory address to
which control may be transferred if a branch is to be taken.
5.2.9 Base Relative (B)
There are two formats which implement Base Relative
Addressing; one allows indexing and one does not. For the non-
indexable form the contents of the instruction specified base
register (BR = BR' + 12) is added to the 8-bit displacement field
(DU) of the 16-bit instruction. For the indexable form, the sum of the
contents of a specified index register (RX) and a specified base
register (BR = BR' + 12) is the address of the required operand.
Registers R1 through R15 may be specified for indexing and the
base register may be R12 through R15.
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