MA17502 Datasheet, PDF (3/30 Pages) Dynex Semiconductor – Radiation Hard MIL-STD-1750A Control Unit

MA17502
As shown in Figure 1, the MAS281 is the minimum
processor configuration consisting of an Execution Unit, a
Control Unit, and an Interrupt Unit. This configuration is
capable of accessing a 64K-word address space. Addition of
an MMU configured MA31751 allows access to a 1M-word
address space. This can also be configured as a BPU to
provide hardware support for 1K-word memory block write
protection.
The CU, as with all components of the MAS281 chip set, is
fabricated with CMOS/SOS process technology. Input and
output buffers associated with signals external to the MAS281
are TTL compatible.
Detailed descriptions of the CU’s companion chips are
provided in separate data sheets. Additional discussions on
chip set system considerations, interconnection details, and the
Digital Avionics lnstruction Set (DAlS) mix benchmarking
analysis are provided in separate applications notes.
2.0 ARCHITECTURE
The Control Unit consists of a microsequencer, an
instruction mapping ROM, a microcode storage ROM, and
various buses. Details of these components are shown in
Figure 2 and are discussed below:
2.1 MICROSEQUENCER
The CU microsequencer is a 12-bit wide microcode address
generator. Major features of the microsequencer include a
microprogram counter (PC), a microprogram counter save
register (PC Save), microcode address increment logic,
instruction pipeline registers IA and IB, an iteration of loop
counter, a next microcode address source multiplexer, and
various pipelining latches. These features are represented in
Figure 2.
The 12-bit microcode address width allows the
microsequencer to access up to 4096 words of microcode. The
MIL-STD-1750A instructions are implemented as sequences of
microinstructions stored within the lower 2048 locations of this
address space. The address for each microinstruction in a
sequence is provided by the next microcode address source
multiplexer. This multiplexer, under control of the CU control
logic, select from one of six next address sources. Sequential,
direct jump, conditional jump, and subroutine address
generation modes are supported.
Sequential addressing is accomplished by providing a path
from the output of the next microcode address multiplexer to an
incrementer and back to the PC register input. Direct jumps are
supported by routing a portion of the microinstruction to one of
the next microcode address source multiplexer inputs.
Conditional jumps are determined in the ALU of the Execution
Unit which communicates the decision to the CU via the T1
signal. The T1 signal enables a portion of the microcode word
to create the new address. Subroutine jumps are accomplished
by loading the contents of the incremented PC register into the
PC Save register and then performing a direct jump. Upon
completion of the subroutine, the contents of the PC Save
register are used as the next microcode address.
A new microinstruction sequence begins when an opcode
residing in the lA or IB register is selected by the next
microcode address source multiplexer and used as an address
to simultaneously access both the CU’s Instruction Mapping
ROM and the Microcode Storage ROM. The instruction
Mapping ROM access provides a pointer which is then used to
update the microprogram counter (PC); the Microcode Storage
ROM access provides the first microinstruction of the
sequence. Remaining microinstructions in a sequence are
accessed through the use of the four address generation
modes discussed above.
Iterative microprogram operations are achieved through the
use of the loop counter. The loop counter may be selectively
loaded from either the AD bus or directly from microcode. This
counter tracks the number of iterations remaining and, when
appropriate, issues a completion signal (CZ). When an iterative
operation is called for, the loop counter is loaded and the CU
control logic repeats a particular microinstruction sequence,
using the four address generation modes discussed above,
until the CZ signal is received.
2.2 INSTRUCTION MAPPING ROM
The CU instruction mapping ROM provides 512 8-bit words
of microcode instruction vector storage. The address space of
this ROM is mapped into a portion of the microcode storage
ROM’s address space. Hence, both ROMs are accessed
whenever the microcode address falls within this range. The
eight bits from the instruction mapping ROM serve as-the lower
eight bits of a 12-bit microcode address; the upper four bits are
a hardwired constant. The 12-bit microcode address formed
from the 4-bit constant and the mapping ROM’s eight bits are
loaded into the PC register of the microsequencer and serve as
a means to access nonsequential microcode addresses within
the address space allocated to both the instruction mapping
and microcode storage ROMs.
2.3 MICROCODE ROM
The CU microcode ROM provides 2K (2048) 40-bit words of
storage capacity. All of the microcode required to implement
the full MIL-STD-1750A lnstruction Set Architecture (lSA) fits in
one such ROM.
2.4 BUSES
A 16-bit multiplexed Address/Data (AD) bus provides a
communications path between the CU, the other components
of the MAS281 chip set, the MA31751 MMU/BPU, and any
other devices mapped into the chip set’s address space. The
CU receives MIL-STD-1750A instructions, accessed from
system memory, over this bus and loads them into its
instruction pipeline registers.
A 20-bit multiplexed Microcode (M) bus provides a pathway
between the CU chip and the microcode decode logic on all
other chips which are under CU microcode control. The 40-bit
wide microinstructions from the CU’s microcode ROM are
multiplexed on chip as two 20-bit words and presented on the
interchip M bus during alternate phases of CLK02N. Microcode
bits 39 through 20 are placed on the M bus during the CLK02N
low phase and bits 19 through 0 during the high phase of
CLK02N. The M bus is bidirectional to permit microcode
memory expansion.
A 12-bit microcode address (CC) bus is used to route
microcode addresses from the next microcode address source
multiplexer to the microcode and instruction mapping ROMs as
shown in Figure 2.
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