MA17502 Datasheet, PDF (4/30 Pages) Dynex Semiconductor – Radiation Hard MIL-STD-1750A Control Unit

MA17502
3.0 INTERFACE SIGNALS
All signal definitions are shown in Table 1. In addition, each
of these functions is provided with Electrostatic Discharge
(ESD) protection diodes. All unused inputs must be held to their
inactive state via a connection to VDD or GND.
Throughout this data sheet, active low signals are denoted
by either a bar over the signal name or by following the name
with an “N” suffix. e.g. HOLDN. Referenced signals that are not
found on the MA17502 are preceded by the originating chip’s
functional acronym in parentheses, e.g. (IU)DMAKN.
A description of each pin function, grouped according to
functional interface, follows. The function acronym is presented
first, followed by its definition, its type, and its detailed
description. Function type is either input, output, high
impedance (Hi-Z), or a combination thereof. Timing
characteristics of each of the functions described are provided
in Section 6.0.
3.1 POWER INTERFACE
The power interface consists of a single 5V VDD connection
and two common GND connections.
3.2 CLOCKS
The clock interface, discussed below, is the means by
which the synchronous, microcoded operation of the MAS281
is driven.
3.2.1 Precharge Clock (CLKPCN)
Input. The MA17501 Execution Unit (EU), generates the
CLKPCN signal for the Control Unit. The Control Unit uses this
signal for most of its internal sequencing. During the low phase
of CLKPCN, the internal M Bus is precharged to the high state
to accelerate its response.
The normal CLKPCN period is defined by five OSC cycles
(two cycles low and three cycles high). When a microcode
branch is indicated by the EU, the low state of CLKPCN is
extended to three OSC cycles. During execution of Interrupt
Unit decoded XlO and microcode commands, the high state of
CLKPCN is extended to four OSC cycles. Also, during external
bus cycles, RDYN may be used to cause the EU to prolong the
high state of CLKPCN to greater than three OSC cycles; this
allows the MAS281 chip set to interface with slower external
memory or input/output devices.
During DMA ((IU)DMAKN is low) or Hold ((EU)HLDAKN is
low), CLKPCN will remain low until the CPU takes control
again.
Also, during external bus cycles, RDYN may be used to cause
the EU to prolong the CLK02N trailing low state to greater than
one OSC cycle; this allows the MAS281 chip set to interface
with slower external memory or inpuVoutput devices.
During DMA ((IU)DMAKN is low) or Hold ((EU)HLDAKN is
low), CLKPCN will remain low until the CPU takes control
again.
3.3 BUSES
The following is a discussion of the communication buses
connecting the three-chip set. The AD Bus and M Bus are
mainly operand transfer buses, while the CC Bus is strictly for
providing microcode addresses to auxiliary CUs.
3.3.1 Address/Data Bus (AD Bus)
Input. These signals comprise the multiplexed address and
data bus. During external bus operations, the AD bus
accommodates the transfer of instructions, from memory and
l/O ports, to the MA17502. During internal bus operations, the
AD bus provides additional data to the Control Unit from the
Execution Unit. AD00 is the most significant bit position and
AD15 is the least significant bit position of both the 16-bit data
and 16-bit address. A high on this bus corresponds to a logic 1
and a low corresponds to a logic 0. lnformation on the AD Bus is
clocked into the CU by the high-to-low transition of CLKPCN.
3.3.2 Microcode Bus (M Bus)
Input/Output/Hi-z. The M Bus is the 20-bit multiplexed
microcode bus. The 40-bit microcode instruction is multiplexed
onto the M Bus as two 20-bit words (µW1 and µW2). The first
half of the microcode word, µW1 (bits 39 through 20), is
assured valid on the high-to-low transition of CLK02N and µW2
(bits 19 through 0) is assured valid on the high-to-low transition
of CLKPCN. M00 corresponds to microcode bit 0 (µW1) or 20
(µW2) while M19 corresponds to microcode bit 19 (µW1) or 39
(µW2). A high level indicates a logic 1 and a low level indicates
a logic 0. A high level on CS allows the Control Unit to distribute
microcode over this bus, a low level places the bus in the high
impedance state.
During DMA or Hold states, CLKPCN is held low, thus
holding the internal M bus in the precharged state. Precharging
the internal M Bus forces the 20 bits of the external M Bus low.
3.3.3 Microcode Address Bus (CC Bus)
Input/Output/Hi-Z. The CC bus is provided for future
expansion and is left unconnected.
3.2.2 Phase 2 Clock (CLK02N)
Input. The MA17501 generates the CLK02N signal for the
Control Unit. The CU then uses this signal, in conjunction with
CLKPCN, to control the distribution of microcode on the M Bus.
CLK02N is used to multiplex the 40-bit microcode instruction
into two 20-bit words (µW1 and µW2). The high-to-low edge of
CLK02N switches µW1 (bits 39 through 20) off the M Bus while
switching µW2 (bits 19 through 0) onto the M Bus.
The normal CLK02N period is defined by five OSC cycles
(one cycle low, three cycles high, one cycle low). When a
microcode branch is indicated by the EU, the high state of
CLK02N is extended to four cycles. During execution of
Interrupt Unit decoded XIO and microcode commands, the
trailing low state of CLK02N is extended to two OSC cycles.
3.4 SEQUENCER CONTROL
The following is a discussion of the microsequencer control
input signals. These signals support chip set functions that
require microcode branching based on the results of operations
performed in the Execution or Interrupt Units.
3.4.1 Interrupt Request (IRN)
Input. A low on this input directs the CU to service pending
interrupt requests latched by the Interrupt Unit (IU). Upon
completion of the currently executing MIL-STD-1750A
instruction, the CU checks the IRN input. If IRN is low, then the
CU sequencer will branch to the microcoded interrupt service
routine; else the next MIL-STD-1750A instruction is mapped to
its microcode routine. The microcoded interrupt service routine
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