MA17502 Datasheet, PDF (19/30 Pages) Dynex Semiconductor – Radiation Hard MIL-STD-1750A Control Unit

5.5 INTERNAL I/O COMMAND SUMMARY
Operation
Command
Code (Hex)
Mnemonic
Cycles*
M
P
B
Implemented in MAS281
Set Fault Register
Set Interrupt Mask
Clear Interrupt request
Enable Interrupts
Disable Interrupts
Reset Pending Interrupt
Set Pending Interrupt Register
Reset Normal Power Up Discrete
Write Status Word
Enable Start-Up ROM
Disable Start-Up ROM
Direct Memory Access Enable
Direct MemoryAccess Disable
Ti mer A Start
Ti mer A Halt
Output Timer A
Reset Trigger-Go
Timer B Start
Timer B Halt
Output Timer B
0401
2000
2001
2002
2003
2004
2005
200A
200E
4004
4005
4006
4007
4008
4009
400A
400B
400C
400D
400E
SFR
SMK
CLIR
ENBL
DSBL
RPI
SPI
RNS
WSW
ESUR
DSUR
DMAE
DMAD
TAS
TAH
OTA
GO
TBS
TBH
OTB
2
3
9
2
3
9
2
3
9
2
3
9
2
3
9
2
3
9
2
3
9
2
3
9
2
3a
8.5a
2
3
9
2
3
9
2
3
9
2
3
9
2
3
9
2
3
9
2
3
9
2
3
9
2
3
9
2
3
9
2
3
9
Read Configuration Word
Read Fault Register Without Clear
Read Interrupt Mask
Read Pending Interrupt Register
Read Status Word
Read and Clear Fault Register
Input Timer A
Input Timer B
8400
8401
A000
A004
A00E
A00F
C00A
C00E
RCW
RFR
RMK
RPIR
RSW
RCFR
ITA
ITB
2
2
4
2
2
4
2
2
4
2
2
4
2
1
4
2
2
4
2
2
4
2
2
4
Implemented in BPU
Memory Protect Enable
Load Memory Protect RAM
Read Memory Protect RAM
4003
50XX
D0XX
MPEN
LMP
RMP
2
4
8
2
4
8
2
3
3
Implemented in MMU
Write Instruction Page Register
Write Operand Page Register
Read Memory Fault Status
Read Instruction Page Register
Read Operand Page Register
51XY
52XY
A00D
D1XY
D2XY
WIPR
WOPR
RMFS
RIPR
ROPR
2
4
8
2
4
8
2
3
3
2
3
3
2
3
3
* M = memory, P = processor (5 OSC cycles), B = processor (6 OSC cycles), a = average if more than one
alternative exists.
Table 6b: Internal I/O Command Summary
MA17502
19/30