MA17502 Datasheet, PDF (15/30 Pages) Dynex Semiconductor – Radiation Hard MIL-STD-1750A Control Unit

MA17502
Cycles*
Operation
Op Code/Ext Mnemonic
Format
M
P
B
LOGICAL
Inclusive Logical OR
E1
3X
4X F
E0
4A 8
ORR
ORB
ORBX
OR
ORIM
R
B
BX
D,DX
IM
1
0
0
2
1
0
2
1
0
3
0
0
2
0
0
Logical AND
E3
3X
4X E
E2
4A 7
ANDR
ANDB
ANDX
AND
ANDM
R
B
BX
D,DX
IM
1
0
0
2
1
0
2
1
0
3
0
0
2
0
0
Exclusive Logical OR
E5
E4
4A 9
XORR
XOR
XORM
R
D,DX
IM
1
0
0
3
0
0
2
0
0
Logical NAND
E7
NR
E6
N
4A B
NIM
R
D,DX
IM
1
1
0
3
1
0
2
1
0
Set Bit
51
SBR
R
1
0
0
50
SB
D,DX
4
1
0
52
SBI
I,IX
5
2
0
Reset Bit
54
RBR
R
1
1
0
53
RB
D,DX
4
1
0
55
RBI
I,IX
5
2
0
Test Bit
57
TBR
R
1
0
0
56
TB
D, DX
3
0
0
58
TBI
I,IX
4
1
0
Test and Set Bit
59
TSB
D,DX
4
0
2
Set Variable Bit in Register
5A
SVBR
R
1
0
1
Reset Variable Bit in Register
5C
RVBR
R
1
1
1
Test Variable Bit in Register
5E
TVBR
R
1
0
1
Store Register Through Mask
97
SRM
D,DX
4
3
0
BYTE
Load From Upper Byte
8B
8D
Load From Lower Byte
8C
8E
Store Into Upper Byte
9B
9D
Store Into Lower Byte
9C
9E
Exchange Bytes in Register
EC
LUB
LUBl
LLB
LLBI
STUB
SUBI
STLB
SLBI
XBR
D,DX
I,IX
D,DX
I,IX
D,DX
I, IX
D,DX
I,IX
S
3
0
0
4
1
0
3
1
0
4
2
0
4
1
0
5
3
0
4
1
0
5
2
0
1
0
1
* M = memory, P = processor (5 OSC cycles), B = processor (6 OSC cycles), a = average if more than one alternative exists.
Table 6a (continued): Instruction Summary
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