BCM43362KUBG Datasheet, PDF (79/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ b/g/n MAC/Baseband/Radio + SDIO

BCM43362 Data Sheet
gSPI Signal Timing
The gSPI device always samples data on the rising edge of the clock.
Figure 27: gSPI Timing
gSPI Signal Timing
Table 26: gSPI Timing Parameters
Parameter
Symbol Minimum
Maximum
Units Note
Clock period
Clock high/low
Clock rise/fall time
Input setup time
Input hold time
Output setup time
Output hold time
CSX to clock^a
Clock to CSX^c
T1
T2/T3
T4/T5
T6
T7
T8
T9
–
–
20.8
–
ns
(0.45 × T1) – T4 (0.55 × T1) – T4 ns
–
2.5
ns
5.0
–
ns
5.0
–
ns
5.0
–
ns
5.0
–
ns
7.86
–
ns
–
–
ns
F_max = 48 MHz
–
–
Setup time, SIMO valid to
SPI_CLK active edge
Hold time, SPI_CLK active
edge to SIMO invalid
Setup time, SOMI valid before
SPI_CLK rising
Hold time, SPI_CLK active
edge to SOMI invalid
CSX fall to 1st rising edge
Last falling edge to CSX high
a. SPI_CSx remains active for entire duration of gSPI read/write/write_read transaction (i.e., overall words for
multiple word transaction)
Broadcom_®
February 13, 2015 • 43362-DS106-R
IEEE 802.11 b/g/n MAC/Baseband/Radio + SDIO
Page 78
BROADCOM CONFIDENTIAL