BCM43362KUBG Datasheet, PDF (14/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ b/g/n MAC/Baseband/Radio + SDIO

BCM43362 Data Sheet
Power Supplies and Power Management
Section 2: Power Supplies and Power
Management
WLAN Power Management
The BCM43362 has been designed with the stringent power consumption requirements of mobile devices in
mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell
libraries were chosen to reduce leakage current and supply voltages. Additionally, the BCM43362 integrated
RAM is a low-leakage memory with dynamic clock control. The dominant supply current consumed by the RAM
is leakage current only.
Additionally, the BCM43362 includes an advanced WLAN power management unit (PMU) sequencer. The PMU
sequencer provides significant power savings by putting the BCM43362 into various power management states
appropriate to the current environment and activities that are being performed. The power management unit
enables and disables internal regulators, switches, and other blocks based on a computation of the required
resources and a table that describes the relationship between resources and the time needed to enable and
disable them. Power-up sequences are fully programmable. Configurable, free-running counters, which run on
the 32.768 kHz low-power oscillator (LPO) sleep clock in the PMU sequencer, are used to turn individual
regulators and power switches on and off. Clock speeds are dynamically changed, or gated off, as appropriate
for the current mode. Slower clock speeds are used wherever possible.
The BCM43362 power states are described as follows:
• Active mode—All components in the BCM43362 are powered up and fully functional with active carrier
sensing and frame transmission and receiving. All required regulators are enabled and put in the most
efficient mode (PWM or Burst) based on the load current. Clock speeds are dynamically adjusted by the
PMU sequencer.
• Sleep mode—The radio, AFE, PLLs, and the crystal oscillator are powered down. The rest of the
BCM43362 remains powered up in an IDLE state. All main clocks are shut down. The 32.768-kHz LPO
sleep clock is available only for the PMU sequencer. This condition is necessary to allow the PMU
sequencer to wake up the chip and transition to Active mode. In Sleep mode, the primary power consumed
is due to leakage current.
• Power-down modes—The BCM43362 has a full power-down mode and a low-power shutdown mode. A
full power-down occurs when there is no VIO voltage, and WL_RST_N and EXT_SMPRS_REQ are low. A
low-power shutdown occurs when VIO is present, and WL_RST_N and EXT_SMPRS_REQ are low. In low-
power shutdown, only the band gap and LDO3P3 are on. Both power-down modes are exited when the
host asserts either WL_RST_N or EXT_SMPS_REQ high.
• External mode—In this mode, the following are true:
– The assertion of EXT_SMPS_REQ turns only the Core Buck (CBUCK) regulator on.
– The WLAN is in reset (WL_RST_N = low).
– The state of LDO3P3 and the band gap are dependent on VBAT and VIO.
Broadcom_®
February 13, 2015 • 43362-DS106-R
IEEE 802.11 b/g/n MAC/Baseband/Radio + SDIO
Page 13
BROADCOM CONFIDENTIAL