BCM43362KUBG Datasheet, PDF (28/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ b/g/n MAC/Baseband/Radio + SDIO

BCM43362 Data Sheet
Generic SPI Mode
Command Structure
The gSPI command structure is 32 bits. The bit positions and definitions are as shown in Figure 12.
Figure 12: gSPI Command Structure
BCM_SPID Command Structure
31 30 29 28 27
C A F1 F0
Address – 17 bits
11 10
0
Packet length - 11bits *
* 11’h0 = 2048 bytes
Function No: 00 – Func 0: All SPI specific registers
01 – Func 1: Registers and meories belonging to other blocks in the chip (64 bytes max)
10 – Func 2: DMA channel 1. WLAN packets up to 2048 bytes.
11 – Func 3: DMA channel 2 (optional). Packets up to 2048 bytes.
Access : 0 – Fixed address
1 – Incremental address
Command : 0 – Read
1 – Write
Write
The host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the CS
going low. The following bits are clocked out on the falling edge of the gSPI clock. The device samples the data
on the active edge.
Write/Read
The host reads on the rising edge of the clock requiring data from the device to be made available before the
first rising clock edge of the clock burst for the data. The last clock edge of the fixed delay word can be used to
represent the first bit of the following data word. This allows data to be ready for the first clock edge without
relying on asynchronous delays.
Read
The read command always follows a separate write to set up the WLAN device for a read. This command differs
from the write/read command in the following respects: a) chip selects go high between the command/address
and the data and b) the time interval between the command/address is not fixed.
Broadcom_®
February 13, 2015 • 43362-DS106-R
IEEE 802.11 b/g/n MAC/Baseband/Radio + SDIO
Page 27
BROADCOM CONFIDENTIAL