BCM43362KUBG Datasheet, PDF (21/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ b/g/n MAC/Baseband/Radio + SDIO

BCM43362 Data Sheet
TCXO
Table 2: Crystal Oscillator and External Clock Requirements and Performance
Crystal
External Frequency
Reference
Parameter
Conditions/Notes
Min Typ Max Min Typ Max
Units
Frequency
–
Between 12 MHz and 52 MHz^a
Crystal load
–
capacitance
– 12 –
ESR
–
––
60
Input Impedance
(OSCIN)^b
Resistive
Capacitive
30k 100k –
–
– 7.5
Input Impedance
(WRF_TCXO_IN)
Resistive
Capacitive
30k 100k –
–
–4
OSCIN input voltage AC-coupled analog signal
400 – 1200
OSCIN input low level DC-coupled digital signal
0
– 0.2
OSCIN input high level DC-coupled digital signal
1.0 – 1.36
WRF_TCXO_IN input _{DC-coupled analog signal}^c
voltage
400 –
TCXO_
VDD^d
Frequency tolerance –
Initial + over
temperature
–20 –
20 –20 – 20
Duty cycle
26 MHz clock
40 50 60
Phase Noise^{e, f}
(IEEE 802.11 b/g)
26 MHz clock at 1 kHz offset
26 MHz clock at 10 kHz offset
26 MHz clock at 100 kHz offset
–
–
– 119
–
–
– 129
–
–
– 134
26 MHz clock at 1 MHz offset
–
–
– 139
Phase Noise^{e, f}
(IEEE 802.11n,
2.4 GHz)
26 MHz clock at 1 kHz offset
26 MHz clock at 10 kHz offset
26 MHz clock at 100 kHz offset
–
–
– 124
–
–
– 134
–
–
– 139
26 MHz clock at 1 MHz offset
–
–
– 144
pF
Ω
Ω
pF
Ω
pF
mV_p-p
V
V
mV_p-p
ppm
%
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
a. The frequency step size is approximately 80 Hz. The BCM43362 does not auto-detect the reference clock
frequency; the frequency is specified in the software/NVRAM file.
b. The internal clock buffer connected to this pin will be turned off when the BCM43362 goes into Sleep mode.
When the clock buffer turns on and off, there will be a small impedance variation up to ±15%.
c. This input has an internal DC blocking capacitor, so do not include an external DC blocking capacitor.
d. The maximum allowable voltage swing for the WRF_TCXO_IN input is equal to the WRF_TCX0_VDD3P3
supply voltage range, which is 1.7V to 3.3V.
e. For a clock reference other than 26 MHz, 20 × log10(f/26) dB should be added to the limits, where f = the
reference clock frequency in MHz.
f. If the selected clock has a flat phase-noise response above 100 kHz, then it is acceptable to subtract 1 dB from
all 1 kHz, 10 kHz, and 100 kHz values shown, and ignore the 1 MHz requirement.
Broadcom_®
February 13, 2015 • 43362-DS106-R
IEEE 802.11 b/g/n MAC/Baseband/Radio + SDIO
Page 20
BROADCOM CONFIDENTIAL