CY8C27 Datasheet, PDF (45/332 Pages) –

CY8C27xxx Preliminary Data Sheet
3 CPU Core (M8C)
Destination Indirect Post Increment Example:
Source Code
MVI
[8], A
Machine Code
3F 08
Comments
The value in memory at address 8 (the indirect address) points to a
memory location in RAM. The Accumulator value is moved into the
memory location pointed to by the indirect address. The indirect
address in memory, at address 8, is then incremented.
3.6 Register Definitions
3.6.1 CPU_F (Flag) Register
The Flag register has four chip dependent bits (FL[7:4]) and
four dedicated bits (FL[3:0]), as shown in Table 3-1.
3.6.1.1 Chip-dependent Flag Bits
The chip-dependent Flag bits have no effect internally on
the M8C. These bits are manipulated by the user with the
Flag-Logic opcodes (for example, XOR F, 80h). Bit Defini-
tions for the PSoC Mixed Signal Array family are as follows.
Bits 7, 6, and 5: Reserved.
Bit 4: IOX. IO Bank Select. This bit is used to select
between register banks, in order to support more than 256
registers.
3.6.1.2 Dedicated Flag Bits
The dedicated Flag bits are described as follows.
Bit 3: Reserved.
Bit 2: Carry. Carry Flag. This bit is set or cleared in
response to the result of several instructions. It may also be
manipulated by the Flag-Logic opcodes (for example, OR F,
4). See the PSoC Designer Assembly Guide User Manual
for more details.
Bit 1: Zero. Zero Flag. This bit is set or cleared in response
to the result of several instructions. It may also be manipu-
lated by the Flag-Logic opcodes (for example, OR F, 2). See
the PSoC Designer Assembly Guide User Manual for more
details.
Bit 0: GIE. Global Interrupt Enable. The state of this bit
determines whether interrupts (by way of the IRQ) will be
recognized by the M8C. This bit is set or cleared by the user,
using the Flag-Logic opcodes (e.g., OR F, 1). GIE is also
cleared automatically by the interrupt routine, after the flag
byte has been stored on the stack.
For GIE=1, the M8C samples the IRQ input for each instruc-
tion. For GIE=0, the M8C ignores the IRQ.
For additional information, reference the CPU_F register on
page 152.
June 2, 2003
Document #: 38-12012 Rev. **
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