CY8C27 Datasheet, PDF (37/332 Pages) –

3 CPU Core (M8C)
This chapter explains the CPU Core, called M8C, and its associated registers. It covers the internal M8C registers, address
spaces, instruction formats, and addressing modes.
Table 3-1. M8C Registers
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
M8C Register
x,F7h
CPU_F
IOX
Carry
Zero
Related Registers
1,E0h
OSC_CR0 32k Select PLL Mode No Buzz
Sleep[1:0]
CPU Speed[2:0]
x,FF
CPU_SCR0
GIES
WDRS
PORS
Sleep
LEGEND
L: The AND and OR flag instructions can be used to modify this register.
x: An “x” before the coma in the address field indicates that this register can be accessed or written to no matter what bank is used.
Bit 0
GIE
STOP
Access
RL : 00
RW : 00
W : 17
The M8C is a four MIPS 8-bit Harvard architecture micropro-
cessor. Code selectable processor clock speeds from 93.7
kHz to 24 MHz allow the M8C to be tuned to a particular
application’s performance and power requirements. The
M8C supports a rich instruction set which allows for efficient
low-level language support.
3.1 Internal Registers
The M8C has five internal registers that are used in program
execution. The following is a list of these registers.
s Accumulator (A)
s Index (X)
s Program Counter (PC) – internal use only
s Stack Pointer (SP)
s Flags (F)
All of the internal M8C registers are eight bits in width except
for the PC which is 16 bits wide. Upon reset, A, X, PC, and
SP are reset to 0x00. The Flag register (F) is reset to
0x02, indicating that the Z flag is set.
With each stack operation, the SP is automatically incre-
mented or decremented so that it always points to the next
stack byte in RAM. If the last byte in the stack is at address
0xFF the Stack Pointer will wrap to RAM address 0x00. It
is the firmware developer’s responsibility to ensure that the
stack does not overlap with user-defined variables in RAM.
With the exception of the F register, the M8C internal regis-
ters are not accessible via an explicit register address. The
internal M8C registers are accessed using instructions such
as:
s MOV A, expr
s MOV X, expr
s SWAP A, SP
s OR F, expr
s JMP
The F register may be read by using address 0xF7 in either
register bank.
3.2 Address Spaces
The M8C has three address spaces: ROM, RAM, and regis-
ters. The ROM address space includes the supervisory
ROM (SROM) and the Flash. The ROM address space is
accessed via its own address and data bus. Figure 3-1 illus-
trates the arrangement of the PSoC microcontroller address
spaces.
The ROM address space is composed of the Supervisory
ROM and the on-chip Flash program store. Flash is orga-
nized into 64-byte blocks. The user need not be concerned
with program store page boundaries, as the M8C automati-
cally increments the 16-bit PC on every instruction making
the block boundaries invisible to user code. Instructions
occurring on a 256-byte Flash page boundary (with the
exception of jmp instructions) incur an extra M8C clock
cycle as the upper byte of the PC is incremented.
The register address space is used to configure the PSoC
microcontroller’s programmable blocks. It consists of two
June 2, 2003
Document #: 38-12012 Rev. **
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