CY8C27 Datasheet, PDF (237/332 Pages) –

CY8C27xxx Preliminary Data Sheet
18 Analog Interface
18.1.2 Analog Comparator Bus Interface
Each analog column has a dedicated comparator bus asso-
ciated with it. Every analog PSoC block has a comparator
output that can drive this bus. However, only one analog
block in a column can actively drive the comparator bus for a
column at any one time. The output on the comparator bus
can drive into the digital blocks as a data input. It also
serves as an input to the decimator, as an interrupt input,
and is available as read-only data in the Analog Comparator
Control Register (CMP_CR0, Address = Bank 0,64H).
Data
Output
from
DBB01
Data
Output
from
DCB02
Data
Output
from
DBB11
Data
Output
from
DCB12
Incremental Gate Input
Multiplexer, one per
device
(From Digital Blocks)
One Analog Column
Continuous Time Block
CMP
Latch
Transparent, PHI1 or PHI2
CBUS
Driver
Switched Capacitor Block
CMP
Latch
PHI1 or PHI2
CBUS
Driver
Switched Capacitor Block
CMP
Latch
PHI1 or PHI2
CBUS
Driver
Analog Comparator Bus Slice
INC SEL
Incremental Gate, one
per column
(From Digital Blocks)
From col (i+1)
Latch
LUT
PHI2
BYPASS
(CLDIS, CMP_CR1[7:4])
To col (i-1)
PHI2
Destinations
1) Comparator
Register
2) Data Inputs for
Digital Blocks
3) Input to
Decimator
Column Interrupt
Output to SAR
Accelerator Input Mux
Figure 18-2. An Analog Comparator Bus Slice
Figure 18-2 illustrates one column of the comparator bus. In
the Continuous Time (CT) analog blocks, the CPhase and
CLatch bits of CT Block Control Register 2 determine
whether the output signal on the comparator bus is latched
inside the block, and if it is, which clock phase it is latched
on. In the Switched Capacitor (SC) analog blocks, the output
on the comparator bus is always latched. The ClockPhase
bit in SC Block Control Register 0 determines the phase on
which this data is latched and available.
The comparator bus is latched before it is available, to either
drive the digital blocks, interrupt, decimator, or be read in the
CMP_CR0 register. The latch for each comparator bus is
transparent (the output tracks the input) during the high
period of PHI2. During the low period of PHI2, the latch
retains the value on the comparator bus during the high-to-
low transition of PHI2. The CMP_CR0 register is shown in
Table 18-1. There is also an option to force the latch in each
column into a transparent mode by setting bits in the
CMP_CR1 register.
As shown in Figure 18-2, the Comparator bus output is
gated by a signal from the digital blocks. This feature is used
to precisely control the integration period of an incremental
ADC. There are two direct connect digital block output
options per row for driving the gate signal: DBBx1 and
June 2, 2003
Document #: 38-12012 Rev. **
237