CY8C27 Datasheet, PDF (290/332 Pages) –

27 I2C
CY8C27xxx Preliminary Data Sheet
Master Transmitter/Receiver
Host issues
Generate
START
command to
I2C_MCR
A Start/Address compete
interrupt is generated.
The SCL line is held low.
Host issues a
command to the
I2C_SCR register
START
7-BIT ADDRESS
R/W
ACK
1
SHIFTER
7
8
9
Host issues ACK/
NACK command to
An interrupt is generated _{the I2C_SCR}
on completed reception
register
of the byte. The SCL line
is held low.
8-BIT DATA
ACK/
NACK
ACK = Host
master wants
more
STOP
1
7
8
9
NACK = Host
master indicates
end-of-data
SHIFTER
Host reads the
received byte from
I2C_DR register
Host writes address
byte to the I2C_DR
register.
Host issues TRANSMIT
command to the
I2C_SCR register
An interrupt is generated
on complettion of the byte
+ ACK/NACK. The SCL
line is held low.
Host issues STOP
command
8-BIT DATA
ACK/
NACK
NACK =
Slave says no
more.
STOP
1
SHIFTER
Host writes a byte to
transmit I2C_DR
register.
7
8
9
ACK = Slave
say OK to
receive more.
Master wants
to send more
bytes
Figure 27-3. Master Operation
27.3 Register Definitions
The I2C block contains four registers, all of which reside in
User IO space: Configuration Register (I2C_CFG), Status
and Control Register (I2C_SCR), Master Status and Control
Register (I2C_MSCR), and Data Register (I2C_DR).
The Configuration register is used to set the basic operating
modes, baud rate, and selection of interrupts. The Status
and Control register is used by both Master and Slave to
control the flow of data bytes and to keep track of the bus
state during a transfer. Data and address bytes are written
to and read from the Data Register. The Master Status and
Control register implements I2C framing controls and pro-
vides Bus Busy status.
27.3.1 I2C_CFG Register
This register is the I2C configuration register and contains
the configuration bits for both Master and Slave mode oper-
ation. These bits control baud rate selection and optional
interrupts. These values are typically set once for a given
configuration. The bits in this register are all R/W.
Table 27-2. I2C_CFG Configuration Register
Bit Access Description
0
R/W
Enable Slave
‘0’ = Disabled
‘1’ = Enabled
1
R/W
Enable Master
‘0’ = Disabled
‘1’ = Enabled
3:2 R/W
Clock Rate
00 = 100K, Standard Mode
01 = 400K Fast Mode
10 = 50K Standard Mode
11 = Reserved
4
R/W
Stop IE
Stop interrupt enable.
0 = Disabled.
1 = Enabled. An interrupt is generated
on the detection of a Stop Condition.
Mode
Master/
Slave
Master/
Slave
Master/
Slave
Master
Only
290
Document #: 38-12012 Rev. **
June 2, 2003