CY8C27 Datasheet, PDF (166/332 Pages) –

13 Register Details
CY8C27xxx Preliminary Data Sheet
13.2.10 ABF_CR0
Analog Output Buffer Control Register 0
Individual Register Names and Addresses
ABF_CR0: 1,62h
Access : POR
Bit Name
7
RW : 0
ACol1Mux
6
RW : 0
ACol2Mux
5
RW : 0
ABUF1EN
4
RW : 0
ABUF2EN
3
RW : 0
ABUF0EN
2
RW : 0
ABUF3EN
1
RW : 0
Bypass
0
RW : 0
PWR
For additional information, reference the “Register Definitions” on page 65 in the Analog Output Drivers chapter or the “Regis-
ter Definitions” on page 255 in the Analog Input Configuration chapter.
Bit
Name
[7]
ACol1Mux
[6]
ACol2Mux
[5]
ABUF1EN
[4]
ABUF2EN
[3]
ABUF0EN
[2]
ABUF3EN
[1]
Bypass
[0]
PWR
Description
0
Set column 1 input to column 1 input mux output
1
Set column 1 input to column 0 input mux output
0
Set column 2 input to column 2 input mux output
1
Set column 2 input to column 3 input mux output
Enables the analog output buffer for Analog Column 1 (Pin P0[5])
0
Disable analog output buffer
1
Enable analog output buffer
Enables the analog output buffer for Analog Column 2 (Pin P0[4])
0
Disable analog output buffer
1
Enable analog output buffer
Enables the analog output buffer for Analog Column 0 (Pin P0[3])
0
Disable analog output buffer
1
Enable analog output buffer
Enables the analog output buffer for Analog Column 3 (Pin P0[2])
0
Disable analog output buffer
1
Enable analog output buffer
Connects the positive input of all four amplifiers directly to their outputs. Amplifiers need to be dis-
abled when in Bypass mode.
Determines power level of all output buffers
0
Low output power
1
High output power
166
Document #: 38-12012 Rev. **
June 2, 2003