CY8C27 Datasheet, PDF (221/332 Pages) –

CY8C27xxx Preliminary Data Sheet
17 Digital Blocks
Free running
internal bit rate
clock is CLK input
divided by two
Setup time
for TX
Buffer write
Shifter is loaded
with first byte
Last bit of received
data is valid on this
edge and is latched
into RX Buffer
Shifter is loaded
with next byte
CLK INPUT
INTERNAL CLOCK
TX REG EMPTY
RX REG FULL
MOSI
SCLK (MODE 2)
SCLK (MODE 3)
D7 D6 D5
D2 D1 D0 D7
User writes first
byte to TX Buffer _{First input}
register
bit latched
First shift
User writes
next byte to TX
Buffer register
Figure 17-17. Typical SPIM Timing in Mode 2 and 3
Status Generation and Interrupts. There are four status
bits in an SPI Block: TX Reg Empty, RX Reg Full, SPI Com-
plete, and Overrun.
TX Reg Empty indicates that a new byte can be written to
the TX Buffer Register. When the block is enabled, this sta-
tus bit is immediately asserted. This status bit is cleared
when the user writes a byte of data to the TX Buffer Regis-
ter. TX Reg Empty is a control input to the state machine
and if a transmission is not already in progress, the asser-
tion of this control signal initiates one. This is the default
SPIM block interrupt. However, an initial interrupt is not gen-
erated when the block is enabled. The user must write a
byte to the TX Buffer register and that byte must be loaded
into the shifter before interrupts generated from the TX Reg
Empty status bit are enabled.
RX Reg Full is asserted on the edge that captures that 8th
bit of receive data. This status bit is cleared when the user
reads the RX Buffer Register (DR2).
Overrun status is set if RX Reg Full is still asserted from a
previous byte when a new byte is about to be loaded into the
RX Buffer register. Because the RX Buffer register is imple-
mented as a latch, Overrun status is set one-half bit clock
before RX Reg Full status.
SPI Complete is an optional interrupt and is generated when
8 bits of data and clock have been sent. In modes 0 & 1, this
occurs one-half cycle after RX Reg Full is set because in
these modes, data is latched on the leading edge of the
clock, and there is an additional one-half cycle remaining to
complete that clock. In modes 2 & 3, this occurs at the same
edge that the receive data is latched. This signal may be
used to read the received byte or it may be used by the
SPIM to disable the block after data transmission is com-
plete.
See Figure 17-18 and Figure 17-19 for status timing rela-
tionships.
June 2, 2003
Document #: 38-12012 Rev. **
221