CY8C27 Datasheet, PDF (200/332 Pages) –

16 Row Digital Interconnect (RDI)
CY8C27xxx Preliminary Data Sheet
between a lookup table’s four configuration bits and the
resulting logic function. Some users may find it easier to
determine the proper configuration bits setting by remem-
bering that the configuration’s bits represent the output col-
umn of a two input logic truth table. Table 16-5 lists seven
examples of the relationship between the LUT’s output col-
umn for a truth table and the LUTx[3:0] configuration bits.
Table 16-5. Example LUT Truth Tables
AB
0
0
0
1
1
0
1
1
LUTx[3:0]
AND
0
0
0
1
0001
OR
0
1
1
1
0111
A+B
1
0
1
1
1011
A&B
0
0
1
0
0010
A
0
0
1
1
0011
B
0
1
0
1
0101
True
1
1
1
1
1111
Table 16-6. RDIxLTx Register
LUTx[3:0]
0x0: 0000: FALSE
0x1: 0001: A .AND. B
0x2: 0010: A .AND. B
0x3: 0011: A
0x4: 0100: A .AND. B
0x5: 0101: B
0x6: 0110: A .XOR. B
0x7: 0111: A .OR. B
0x8: 1000: A .NOR. B
0x9: 1001: A .XNOR. B
0xA: 1010: B
0xB: 1011: A .OR. B
0xC: 1100: A
0xD: 1101: A .OR. B
0xE: 1110: A. NAND. B
0xF: 1111: TRUE
put lines. Table 16-7 lists the meaning for each of the row
output bits (ROx[3:0]).
Table 16-7. RDIxROx Register
ROx[0]
ROx[1]
ROx[2]
ROx[3]
0: do not drive out
1: drive GOE[0,1,2,3]
0: do not drive out
1: drive GOE[4,5,6,7]
0: do not drive out
1: drive GOO[0,1,2,3]
0: do not drive out
1: drive GOO[4,5,6,7]
For additional information, reference the RDIxRO0 register
on page 125 and the RDIxRO1 register on page 126.
16.3 Timing Diagrams
SYSCLK
Set up to positive edge.
GLOBAL INPUT
ROW INPUT
Output of the synchronizer changes on the second
positive edge that follows the input transition.
Figure 16-3. Optional Row Input Synchronization to
SYSCLK
For additional information, reference the RDIxLT0 register
on page 123 and the RDIxLT1 register on page 124.
16.2.5 RDIxROx Registers
The final configuration bits for outputs from Digital PSoC
Rows are in the two RDIxROx registers. These registers
hold the 16 bits and can individually enable the tri-state buff-
ers that connect to all eight of the Global Output Even lines
and all eight of the Global Output Odd lines. This means that
any row can drive any global output. Keep in mind that tri-
state drivers are being used to drive the global output lines;
therefore, it is possible for a part, with more than one Digital
PSoC Row, to have multiple drivers on a single global output
line. It is the user’s responsibility to ensure that the part is
not configured with multiple drivers on any of the global out-
200
Document #: 38-12012 Rev. **
June 2, 2003