CY8C27 Datasheet, PDF (136/332 Pages) –

13 Register Details
13.1.48 INT_MSK0
Interrupt Mask Register 0
CY8C27xxx Preliminary Data Sheet
Individual Register Names and Addresses
INT_MSK0: 0,E0h
Access : POR
Bit Name
7
RW : 0
VC3
6
RW : 0
Sleep
5
RW : 0
GPIO
4
RW : 0
Analog 3
3
RW : 0
Analog 2
2
RW : 0
Analog 1
1
RW : 0
Analog 0
0
RW : 0
V Monitor
Note that when an interrupt is masked off, mask bit is ‘0’. The interrupt will still post in the interrupt controller. Therefore, clear-
ing the mask bit only prevents a posted interrupt from becoming a pending interrupt. For additional information, reference the
“Register Definitions” on page 54 in the Interrupt Controller chapter.
Bit
Name
[7]
VC3
[6]
Sleep
[5]
GPIO
[4]
Analog 3
[3]
Analog 2
[2]
Analog 1
[1]
Analog 0
[0]
V Monitor
Description
0
Mask VC3 interrupt.
1
Unmask VC3 interrupt.
0
Mask sleep interrupt.
1
Unmask sleep interrupt.
0
Mask GPIO interrupt.
1
Unmask GPIO interrupt.
0
Mask analog interrupt, column 3.
1
Unmask analog interrupt.
0
Mask analog interrupt, column 2.
1
Unmask analog interrupt.
0
Mask analog interrupt, column 1.
1
Unmask analog interrupt.
0
Mask analog interrupt, column 0.
1
Unmask analog interrupt.
0
Mask voltage monitor interrupt.
1
Unmask voltage monitor interrupt.
136
Document #: 38-12012 Rev. **
June 2, 2003