CY8C27 Datasheet, PDF (207/332 Pages) –

CY8C27xxx Preliminary Data Sheet
17 Digital Blocks
the modular format by subtracting each tap from the MS tap
as shown in the following example.
To implement a 7-bit PRS of length 127, one possible code
is [7,6,4,2]s, which is in simple format. The modular format
would be [7,7-2,7-4,7-6]m or [7,5,3,2]m. Determining the
polynomial to program is similar to the CRC example above.
Set a binary bit for each tap (with bit 0 of the register corre-
sponding to tap 1). Therefore, the code [7,5,3,2] would cor-
respond to 01010110 or 56h.
In both the CRC and PRS cases, an appropriate Seed value
should be selected that is greater than or equal in bit length.
17.1.8.1 Usability Exceptions
The following are usability exceptions for the CRCPRS func-
tion.
1. The polynomial register must only be written when the
block is disabled.
17.1.8.2 Block Interrupt
The CRCPRS has one fixed interrupt source, which is the
compare auxiliary output.
17.1.9 SPI Protocol Function
The Serial Peripheral Interface (SPI) is a Motorola specifica-
tion for implementing full-duplex synchronous serial commu-
nication between devices. The 3-wire protocol uses both
edges of the clock to enable synchronous communication,
without the need for stringent setup and hold requirements.
Figure 17-5 shows the basic signals in a simple connection.
MISO MOSI
SCLK
SS_
MOSI MISO
SCLK
SS_
SPI Master
SPI Slave
Data is
output by
both the
Master and
Slave, on
one edge of
the clock.
SCLK
MOSI
MISO
Data is
registered at
the input of
both devices,
on the
opposite edge
of the clock.
Figure 17-5. Basic SPI Configuration
A device can be a Master or Slave. A Master outputs clock
and data to the Slave device and inputs Slave data. A Slave
device inputs clock and data from the Master device and
outputs data for input to the Master. The Master and Slave
together are essentially a circular shift register, where the
Master is generating the clocking and initiating data trans-
fers.
A basic data transfer occurs when the Master sends 8 bits of
data, along with eight clocks. In any transfer, both Master
and Slave are transmitting and receiving simultaneously. If
the Master is only sending data, the received data from the
Slave is ignored. If the Master wishes to receive data from
the Slave, the Master must send dummy bytes to generate
the clocking for the Slave to send data back.
17.1.9.1 SPI Protocol Register Definitions
The SPI Protocol register definitions are located in Table 17-
4. The use of the SS_ signal varies according to the capabil-
ity of the Slave device.
Table 17-4. SPI Protocol Register Descriptions
Name
MOSI
MISO
SCLK
SS_
Function
Description
Master Out Master data output.
Slave In
Master In Slave data output.
Slave Out
Serial Clock Clock generated by the Master.
Slave Select
(active low)
This signal is provided to enable multi-slave
connections to the MISO pin. The MOSI and
SCLK pins can be connected to multiple
slaves, and the SS_ input selects which slave
will receive the input data and drive the MISO
line.
17.1.10 SPI Master Function
The SPI Master (SPIM) offers SPI operating modes 0-3. By
default, the MSB of the data byte is shifted out first. An addi-
tional option can be set to reverse the direction and shift the
data byte out LSB first.
When configured for SPIM, DR0 functions as a shift register,
with input from the DATA input (MISO) and output to the pri-
mary output F1 (MOSI). DR1 is the TX Buffer register and
DR2 is the RX Buffer register.
The SPI protocol requires data to be registered at the device
input, on the opposite edge of the clock that operates the
output shifter. An additional register (RXD), at the input to
the DR0 shift register, has been implemented for this pur-
pose. This register stores received data for one-half cycle,
before it is clocked into the shift register.
The SPIM controls data transmission between master and
slave because it generates the bit clock for internal clocking
and for clocking the SPIS. The bit clock is derived from the
CLK input selection. Since the PSoC system clock genera-
tors produce clocks with varying duty cycles, the SPIM
divides the input CLK by two to produce a bit clock with a
fifty percent duty cycle. This clock is gated, to provide the
SCLK output on the auxiliary output, during byte transmis-
sions.
There are four control bits and four status bits in the Control
register that provide for host interfacing and synchroniza-
tion.
The SPIM hardware has no support for driving the Slave
Select (SS_) signal. The behavior and use of this signal is
application and chip dependent and, if required, must be
implemented in firmware.
This SPIM function may not be chained.
June 2, 2003
Document #: 38-12012 Rev. **
207