CS42L55 Datasheet, PDF (9/73 Pages) Cirrus Logic – Ultra Low Power, Stereo CODEC w/Class H Headphone Amp

CS42L55
VA
AGND
FILT+
VQ
AFILTA
AFILTB
AIN2A
AIN2B
AIN1A
AIN1B
AIN2REF
AIN1REF
HPDETECT
RESET
VLDO
VDFILT
VL
SDOUT
MCLK
SCLK
GND/
Thermal Pad
17 Analog Power (Input) - Power supply for the internal analog section.
18 Analog Ground (Input) - Ground reference for the internal analog section.
19 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
20 Quiescent Voltage (Output) - Filter connection for the internal quiescent voltage.
21
22
Antialias Filter Connection (Output) - Antialias filter connection for the ADC inputs.
23
25 Analog Input (Input) - The full-scale level is specified in the Analog Input Characteristics specification
26 table.
28
24 Pseudo Diff. Analog Input Reference (Input) - Ground reference for the programmable gain amplifi-
27 ers (PGA).
29
Headphone Detect (Input) - Powers down the left and/or right channel of the line and/or headphone
outputs as described in “Headphone Power Control” on page 43 and “Line Power Control” on page 43.
30 Reset (Input) - The device enters a low power mode when this pin is driven low.
31 Low Dropout Regulator (LDO) Power (Input) - Power supply for the LDO regulator.
32
Low Dropout Regulator (LDO) Filter Connection (Output) - Power supply from the LDO regulator
that provides the low voltage power to the digital section.
33
Digital Interface Power (Input) - Determines the required signal level for the serial audio interface
and I²C control port.
34 Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
35 Master Clock (Input) - Clock source for the delta-sigma modulators.
36 Serial Clock (Input/Output) - Serial clock for the serial audio interface.
-
Ground reference for the internal charge pump and digital section; thermal relief pad. See “QFN Ther-
mal Pad” on page 68 for more information.
1.1 I/O Pin Characteristics
Input and output levels and associated power supply voltage are shown in the table below. Logic levels
should not exceed the corresponding power supply voltage.
Power
Supply
VL
Pin Name
RESET
SCL
SDA
MCLK
LRCK
SCLK
SDOUT
SDIN
VA
HPDETECT
I/O
Input
Input
Input/Output
Input
Input/Output
Input/Output
Output
Input
Input
Internal
Connections
-
-
-
-
Weak Pull-up
(~1 MΩ)
Weak Pull-up
(~1 MΩ)
-
-
-
Driver
-
-
CMOS/Open Drain
-
1.8 V - 3.3 V, CMOS
1.8 V - 3.3 V, CMOS
1.8 V - 3.3 V, CMOS
-
-
Receiver
1.8 V - 3.3 V, with Hysteresis
1.8 V - 3.3 V, with Hysteresis
1.8 V - 3.3 V, with Hysteresis
1.8 V - 3.3 V
1.8 V - 3.3 V
1.8 V - 3.3 V
1.8 V - 3.3 V
1.8 V - 3.3 V
1.8 V - 2.5 V, with Hysteresis
DS773F1
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