CS42L55 Datasheet, PDF (44/73 Pages) Cirrus Logic – Ultra Low Power, Stereo CODEC w/Class H Headphone Amp

6.4.3
SCLK Equals MCLK
Configures the SCLK signal source and speed for master mode.
SCK=MCK[1:0]
00
01
10
11
Output SCLK
Re-timed, bursted signal with minimal speed needed to clock the required data samples
Reserved
MCLK signal after the MCLK divide (MCLKDIV2) circuit
MCLK signal before the MCLK divide (MCLKDIV2) circuit
CS42L55
6.4.4
MCLK Divide By 2
Configures a divide of the input MCLK prior to all internal circuitry.
MCLKDIV2
0
1
Application:
MCLK signal into CODEC
No divide
Divided by 2
“Serial Port Clocking” on page 34
6.4.5
MCLK Disable
Configures the MCLK signal prior to all internal circuitry.
MCLKDIS
0
1
MCLK signal into CODEC
On
Off; Disables the clock tree to save power when the CODEC is powered down.
Note: This function should be enabled during power down (PDN=1) ONLY.
6.5 Clocking Control 2 (Address 05h)
7
Reserved
6
Reserved
5
Reserved
4
SPEED1
3
SPEED0
2
32kGROUP
1
RATIO1
0
RATIO0
6.5.1
Speed Mode
Configures the speed mode of the CODEC in slave mode and sets the appropriate MCLK divide ratio for
LRCK and SCLK in master mode.
SPEED[1:0]
00
01
10
11
Application:
Serial Port Speed
Reserved
Single-Speed Mode (SSM)
Half-Speed Mode (HSM)
Quarter-Speed Mode (QSM)
“Serial Port Clocking” on page 34
Notes:
1. Slave/Master Mode is determined by the M/S bit in “Master/Slave Mode” on page 43.
2. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
(“32 kHz Sample Rate Group” on page 45) and the RATIO[1:0] bits (“Internal MCLK/LRCK Ratio” on
page 45). Low sample rates may also affect dynamic range performance in the typical audio band.
Refer to the referenced application for more information.
44
DS773F1