CS42L55 Datasheet, PDF (24/73 Pages) Cirrus Logic – Ultra Low Power, Stereo CODEC w/Class H Headphone Amp

4.2.1
CS42L55
Pseudo-Differential Inputs
The CS42L55 implements a pseudo-differential input stage. The AINxREF inputs are intended to be used
as a pseudo-differential reference signal. This feature provides 0 noise rejection with single-ended sig-
nals. Figure 10 shows a basic diagram outlining the internal implementation of the pseudo-differential in-
put stage, including a recommended stereo pseudo-differential input topology. If pseudo-differential input
functionality is not required, simply leave the AINxREF pin floating.
// ^{Left Input}
(differential traces)
GND //
// ^{Right Input}
(differential traces)
GND //
1 µF
AIN1A
26
AIN1REF
27
1 µF
1 µF
AIN2B
25
AIN2REF
24
1 µF
PGAAMUX=’0'b
+
PGA A
-
common mode rejection at input of PGA reduces
external system noise
+
PGA B
-
PGABMUX=’1'b
Figure 10. Stereo Pseudo-Differential Input
Referenced Control
Register Location
PGAxMUX ........................... “PGA x Input Select” on page 49
4.2.2
Automatic Level Control (ALC)
When enabled, the ALC monitors the analog input signal after the digital attenuator. The ALC then detects
when peak levels exceed the maximum threshold settings and first lowers the PGA gain settings and then
increases the digital attenuation levels at a programmable attack rate and maintains the resulting level
below the maximum threshold.
When input signal levels fall below the minimum threshold, digital attenuation levels are decreased first
and the PGA gain is then increased at a programmable release rate and maintains the resulting level
above the minimum threshold.
Attack and release rates are affected by the ADC soft ramp/zero cross settings and sample rate, Fs. ALC
soft ramp and zero cross dependency may be independently enabled/disabled.
Recommended settings: Best level control may be realized with the fastest attack and slowest release
setting with soft ramp enabled in the control registers.
Notes:
1. When ALC x is enabled and the PGAxVOL[5:0] is set to +12 dB, the ADCxATT[7:0] should not be set
below 0 dB.
2. The maximum desired gain must be set in the PGAxVOL register. The ALC will only apply the gain
set in PGAxVOL.
3. The ALC maintains the output signal between the MIN and MAX thresholds. As the input signal level
changes, the level-controlled output may not always be the same but will always fall between the
thresholds.
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