CS42L55 Datasheet, PDF (42/73 Pages) Cirrus Logic – Ultra Low Power, Stereo CODEC w/Class H Headphone Amp

CS42L55
6. REGISTER DESCRIPTION
Except for the chip I.D., revision register, and status register, which are Read Only, all registers are Read/Write. See
the following bit definition tables for bit assignment information. The default state of each bit after a power-up se-
quence or reset is listed in each bit description. All Reserved registers must maintain their default state.
I²C Address: 1001010[R/W]
6.1 Fab I.D. and Revision Register (Address 01h) (Read Only)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
REVID2
6.1.1
Chip Revision (Read Only)
CS42L55 revision level.
REVID[2:0]
000
001
Revision Level
A0
A1
1
REVID1
0
REVID0
6.2 Power Control 1 (Address 02h)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
PDN_CHRG
2
PDN_ADCB
1
PDN_ADCA
0
PDN
6.2.1
Power Down ADC Charge Pump
Configures the power state of the ADC charge pump. For optimal ADC performance and power consump-
tion, set to ‘1’b when VA > 2.1 V and set to ‘0’b when VA < 2.1 V.
PDN_CHRG
0
1
ADC Charge Pump Status
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6.2.2
Power Down ADC x
Configures the power state of ADC channel x.
PDN_ADCx
0
1
ADC Status
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6.2.3
Power Down
Configures the power state of the entire CODEC.
PDN
0
1
CODEC Status
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