CS42L55 Datasheet, PDF (37/73 Pages) Cirrus Logic – Ultra Low Power, Stereo CODEC w/Class H Headphone Amp

CS42L55
signal. The zero cross timeout, however, is dependent on the serial port clock domain. Thus, to fully
power down, the ADC must briefly power up to enable the zero cross state machine. Follow the
remaining steps below to complete the power down sequence.
3. Set bit 5 in register 07h to ‘1’b. This implements a high impedance state on the serial output ports to
avoid possible contention in step 4 if clocks are already applied to the serial port.
4. Configure the serial port I/O control for master operation.
Register Controls: M/S
5. Power up either one of the ADC channels.
Register Controls: PDN_ADCx
6. Wait 100 ms.
7. Set the PDN bit to ‘1’b. The CODEC is completely powered down in a low power state.
8. To achieve the lowest operating quiescent current, bring RESET low. All control port registers will be
reset to their default state.
Power Down Sequence Register Location
Step 1a ................................
Step 1b ................................
Step 3 ..................................
Step 4 ..................................
Step 5 ..................................
Step 7 ..................................
“Headphone Volume Control” on page 57, “Line Volume Control” on page 58
“Headphone Channel x Mute” on page 57, “Line Channel x Mute” on page 58
“Miscellaneous Control (Address 07h)” on page 45
“Master/Slave Mode” on page 43
“Power Down ADC x” on page 42
“Power Down” on page 42
4.13 Required Initialization Settings
The current required for various sections in the CODEC must be reduced using the control port compensa-
tion strategy shown below. All performance and power consumption measurements were taken with the
Control Port Compensation shown below.
VA < 2.1 V
1. Write 0x99 to register 0x00.
2. Write 0x30 to register 0x2E.
3. Write 0x07 to register 0x32.
4. Write 0xFF to register 0x33.
VA > 2.1 V
1. Write 0x99 to register 0x00.
2. Write 0x30 to register 0x2E.
3. Write 0x07 to register 0x32.
4. Write 0xFD to register 0x33.
Current adjustments are made in
the following sections:
1. [Enable test register access.]
2. Digital Regulator.
3. ADC.
4. ADC.
5. Write 0xF8 to register 0x34. 5. Write 0xF8 to register 0x34. 5. ADC.
6. Write 0xDC to register 0x35. 6. Write 0xDC to register 0x35. 6. Zero Cross Detector.
7. Write 0xFC to register 0x36. 7. Write 0xF8 to register 0x36. 7. PGA.
8. Write 0xAC to register 0x37. 8. Write 0x6C to register 0x37. 8. PGA.
9. Write 0xF8 to register 0x3A. 9. Write 0xF8 to register 0x3A. 9. DAC.
10. Write 0xD3 to register 0x3C. 10. Write 0xD3 to register 0x3C. 10. Headphone Amplifier.
11. Write 0x23 to register 0x3D. 11. Write 0x23 to register 0x3D. 11. Headphone & Line Amplifier.
12. Write 0x81 to register 0x3E. 12. Write 0x81 to register 0x3E. 12. Line Amplifier.
13. Write 0x46 to register 0x3F. 13. Write 0x46 to register 0x3F. 13. PGA & ADC.
14. Write 0x00 to register 0x00. 14. Write 0x00 to register 0x00. 14. [Disable test register access.].
DS773F1
37