CS42L55 Datasheet, PDF (29/73 Pages) Cirrus Logic – Ultra Low Power, Stereo CODEC w/Class H Headphone Amp

CS42L55
Referenced Control Register Location
HPxVOL[7:0] ....................... “Headphone Volume Control” on page 57
LINExVOL[7:0] .................... “Line Volume Control” on page 58
MSTxVOL[7:0]..................... “Master Volume Control” on page 57
MSTxMUTE......................... “Master Playback Mute” on page 51
AMIXxVOL[6:0].................... “ADC Mixer Channel x Volume” on page 51
PMIXxVOL[6:0].................... “PCM Mixer Channel x Volume” on page 52
AINADV[7:0] ........................ “Analog Input Advisory Volume” on page 59
DINADV[7:0]........................ “Digital Input Advisory Volume” on page 59
BOOSTx .............................. “Boostx” on page 49
ADCxMUX ........................... “ADC x Input Select” on page 46
PGAxVOL............................ “PGAx Volume” on page 49
ADCxMUTE......................... “ADC Mute” on page 48
ADCxSWP........................... “ADC Mix Channel Swap” on page 60
PCMxSWP .......................... “PCM Mix Channel Swap” on page 60
HPxMUX.............................. “Headphone Input Select” on page 47
LINExMUX........................... “Line Input Select” on page 47
HPxMUTE ........................... “Headphone Channel x Mute” on page 57
LINExMUTE ........................ “Line Channel x Mute” on page 58
PDN_HPx ............................ “Headphone Power Control” on page 43
PDN_LINEx ......................... “Line Power Control” on page 43
TREB................................... “Treble Gain” on page 56
BASS................................... “Bass Gain” on page 56
TCEN................................... “Tone Control Enable” on page 56
BEEP................................... “Beep Configuration” on page 55
BPVOL ................................ “Beep Volume” on page 55
ADCB=A .............................. “ADC Channel B=A” on page 48
PGAB=A .............................. “PGA Channel B=A” on page 48
PLYBCKB=A........................ “Playback Channels B=A” on page 50
4.5.1.3 Adapted to Output Signal (Mode 11)
When the Adaptive Power bits are set to 11, the CS42L55 decides which of the two sets of rail voltages
to send to the amplifiers based solely upon the level of the signal being sent to the amplifiers. If the signal
that is sent to the amplifiers would cause the amplifiers to clip when operating on the lower set of rail volt-
ages, the control logic instructs the charge pump to provide the higher set of rail voltages (±VCP) to the
amplifiers. If the signal that is sent to the amplifiers would not cause the amplifiers to clip when operating
on the lower set of rail voltages, the control logic instructs the charge pump to provide the lower set of rail
voltages (±VCP/2) to the amplifiers. This mode of operation eliminates the need to advise the CS42L55
of volume settings external to the device.
Note: Signal detection is made using digital circuitry. This mode should, therefore, not be used with an-
alog passthrough (PGA to HP/Line).
4.5.2
Power Supply Transitions
Charge pump transitions from the lower set of rail voltages to the higher set of rail voltages occur on the
next FLYN/P clock cycle. Despite the fast response time of the system, the capacitive elements on the
VHPFILT pins prevent the rail voltages from changing instantaneously. Instead, the rail voltages ramp up
from ±VCP/2 to ±VCP based on the time constant created by the output impedance of the charge pump
and the capacitor on the VHPFILT pin (the transition time is approximately 20 µs). This behavior is de-
tailed in Figure 15. During this charging transition, a high dv/dt transient on the inputs may briefly clip the
outputs before the rail voltages charge to the full ±VCP level. This transitory clipping has been found to
be inaudible in listening tests.
DS773F1
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