CS42L55 Datasheet, PDF (35/73 Pages) Cirrus Logic – Ultra Low Power, Stereo CODEC w/Class H Headphone Amp

CS42L55
After the PDN bit is released and MCLK is valid, the quiescent voltage, VQ, and the internal voltage refer-
ence, FILT+, will begin powering up to normal operation. The charge pump slowly powers up and charges
the capacitors. Power is then applied to the headphone amplifiers and switched-capacitor filters, and the an-
alog/digital outputs enter a muted state. MCLK occurrences are counted over one LRCK period to determine
a valid MCLK/LRCK ratio and normal operation begins.
4.11
Recommended DAC to HP or Line Power-Up Sequence (Playback)
1. Hold RESET low until the power supplies are stable; no specific power supply sequencing is required.
RESET should be held low for a minimum of 1 ms after power supplies are stable.
2. Apply MCLK (LRCK, SCLK and SDIN may be applied at any time) at the appropriate frequency.
3. Bring RESET high.
4. Wait a minimum of 500 ns before writing to the control port.
5. The default state of the master power down bit, PDN, is ‘1’b. Load the following register settings while
keeping the PDN bit set to ‘1’b.
6. Load the required register settings detailed in 4.13 “Required Initialization Settings” on page 37.
7. Configure the headphone and line power down controls for ON, OFF, or HPDETECT operation.
Register Controls: PDN_HPx[1:0], PDN_LINx[1:0]
8. Configure the serial port I/O control for master or slave operation.
Register Controls: M/S
9. Configure the master clock (MCLK) and bit clock (SCLK) I/O control as desired. Refer to 4.8 “Serial Port
Clocking” on page 34 for the required configuration for a given master clock.
Register Controls: MCLKDIV2, SCK=MCK
10. Configure the sample rate (LRCK) controls for the desired sample rate. Refer to 4.8 “Serial Port Clock-
ing” on page 34 for the required configuration for a given sample rate.
Register Controls: See Register 05h
11. The default state of the DSP engine’s power down bit, PDN_DSP, is ‘0’b. It is not necessary to power
down the DSP before changing the various DSP functions. The DSP may be powered down for addi-
tional power savings.
12. To minimize pops on the headphone or line amplifier, each respective analog volume control must first
be muted and set to maximum attenuation.
Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0]
13. After muting the headphone or line amplifiers, set the PDN bit to ‘0’b.
14. Wait 75 ms for the headphone or line amplifier to power up.
15. Un-mute and ramp the volume for the headphone or line amplifiers to the desired level.
16. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
Power Up Sequence
Register Location
Step 5, 13 ............................
Step 7 ..................................
Steps 8-9 .............................
Step 10 ................................
Step 11 ................................
Step 12a,15a .......................
Step 12b,15b .......................
“Power Down” on page 42
“Power Control 2 (Address 03h)” on page 43
“Clocking Control 1 (Address 04h)” on page 43
“Clocking Control 2 (Address 05h)” on page 44
“Power Down DSP” on page 50
“Headphone Channel x Mute” on page 57, “Line Channel x Mute” on page 58
“Headphone Volume Control” on page 57, “Line Volume Control” on page 58
DS773F1
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