CS42L55 Datasheet, PDF (17/73 Pages) Cirrus Logic – Ultra Low Power, Stereo CODEC w/Class H Headphone Amp

CS42L55
SWITCHING SPECIFICATIONS - SERIAL PORT
Inputs: Logic 0 = GND = AGND, Logic 1 = VL, LRCK, SCLK, SDOUT C_LOAD = 15 pF.
Parameters
Symbol
Min
Max Units
RESET pin Low Pulse Width
MCLK Frequency
MCLK Duty Cycle
Slave Mode (Figure 5)
Input Sample Rate (LRCK)
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Setup Time Before SCLK Rising Edge
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
Master Mode (Figure 6)
Output Sample Rate (LRCK)
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Time Before SCLK Falling Edge
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
(Note 17)
1
-
ms
(See “Serial Port Clocking”
on page 34)
MHz
45
55
%
F_s
(See “Serial Port Clocking”
on page 34)
kHz
45
55
%
1/t_Ps
-
45
68•F_s
Hz
55
%
t_ss(LK-SK)
40
t_ss(SDO-SK)
20
t_hs(SK-SDO)
30
t_ss(SD-SK)
20
t_hs
20
-
ns
-
ns
-
ns
-
ns
-
ns
All Speed Modes
F_s
(See “Serial Port Clocking”
on page 34)
45
55
SCLK = MCLK mode
All Other Modes
RATIO[1:0] = ‘11’
1/t_Pm
1/t_Pm
-
12.0000
-
68•F_s
45
55
RATIO[1:0] = ‘01’ (Note 18)
33
66
t_sm(LK-SK)
-
±2
t_sm(SDO-SK)
20
-
t_hm(SK-SDO)
30
-
t_sm(SD-SK)
20
-
t_hm
20
-
Hz
%
MHz
Hz
%
%
ns
ns
ns
ns
ns
Notes: 17. After powering up the CS42L55, RESET should be held low after the power supplies and clocks are
settled. This specification is valid with the recommended capacitor on VDFILT.
18. The device will periodically extend the SCLK high time to compensate for the fractional MCLK/SCLK
ratio.
LRCK
SCLK
tss(LK-SK)
SDOUT
SDIN
//
//
tP
//
//
tss(SDO-SK)
//
//
tss(SD-SK)
//
//
//
//
ths(SK-SDO)
//
MSB
//
ths
MSB
Figure 5. Serial Port Timing (Slave Mode)
LRCK
SCLK
SDOUT
tsm(LK-SK)
//
//
SDIN
//
//
tPm
//
//
tsm(SDO-SK)
//
//
tsm(SD-SK)
//
//
//
//
thm(SK-SDO)
//
MSB
//
thm
MSB
Figure 6. Serial Port Timing (Master Mode)
DS773F1
17