CS4226_04 Datasheet, PDF (9/37 Pages) Cirrus Logic – Surround Sound Codec

CS4226
SWITCHING CHARACTERISTICS - CONTROL PORT (Inputs: logic 0 = DGND, logic 1 =
VD+, C_L = 30 pF)
Parameter
Symbol
Min
I²C^® Mode (SPI/I²C = 1)
SCL Clock Frequency
f_scl
-
Bus Free Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low Time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 14)
t_hdd
0
SDA Setup Time to SCL Rising
t_sud
250
Rise Time of Both SDA and SCL Lines
t_r
Fall Time of Both SDA and SCL Lines
t_f
Setup Time for Stop Condition
t_susp
4.7
Max
Units
100
kHz
µs
µs
µs
µs
µs
µs
ns
1
µs
300
ns
µs
Notes: 14. Data must be held for sufficient time to bridge the 300 ns transition time of SCL
S/PDIF RECEIVER CHARACTERISTICS (RX1, RX2, RX3, RX4 pins only)
Parameter
Input Resistance
Input Voltage
Input Hysteresis
Input Sample Frequency
CLKOUT Jitter
CLKOUT Duty Cycle (high time/cycle time)
Symbol Min Typ
(Note 15)
Z_N
V_TH
V_HYST
F_S
-
10
200
-
-
50
30
-
-
200
(Note 16)
40
50
Max Units
-
kΩ
-
mVpp
-
mV
50
kHz
-
ps RMS
60
%
Notes: 15. CLKOUT Jitter is for 256×FS selected as output frequency measured from falling edge to falling edge.
Jitter is greater for 384×Fs and 512×Fs as selected output frequency.
16. For CLKOUT frequency equal to 1×Fs, 384×Fs, and 512×Fs. See Master Clock Output section.
DIGITAL CHARACTERISTICS
Parameter
High-level Input Voltage
(except RX1)
Low-level Input Voltage
(except RX1)
High-level Output Voltage at I₀ = -2.0 mA
Low-level Output Voltage at I₀ = 2.0 mA
Input Leakage Current
(Digital Inputs)
Output Leakage Current (High-Impedance Digital Outputs)
Symbol
V_IH
V_IL
V_OH
V_OL
Min
2.8
-0.3
(VD+)-1.0
-
-
-
Typ Max Units
- (VD+)+0.3 V
-
0.8
V
-
-
V
-
0.4
V
-
10
µA
-
10
µA
DS188F4
9