CS4226_04 Datasheet, PDF (25/37 Pages) Cirrus Logic – Surround Sound Codec

CS4226
3.4 Converter Control Byte (02h)
B7
B6
B5
B4
B3
CALP
CLKE
DU
AUTO
LC
B2
B1
B0
0
CAL
RS
RS
Chip reset (Do not clear this bit until all registers have been configured as desired)
0 - No Reset
1 - Reset
CAL
Calibration control bit
0 - Normal operation
1 - Rising edge initiates calibration
LC
Loop Current
0 - Normal Mode, 25 µA PLL loop current (See Figure 1 for filter component values)
1 - High Current Mode, 300 µA PLL loop current (See Figure 1 for filter component values)
The following bits are read only:
AUTO
DU
CLKE
AC3 and MPEG Automatic Detection
0 - No AC3/MPEG Detected
1 - AC3/MPEG detected on RX/AUX
Shows selected De-Emphasis setting used by DAC's
0 - Normal Flat DAC frequency response
1 - De-Emphasis selected
Clocking system status
0 - No errors
1 - PLL is not locked, crystal is not oscillating, or requesting clock change in progress
CALP
Calibration status
1 - Calibration in progress
0 - Calibration done. This register defaults to 01h
This register defaults to 01h
NOTE: The AC3 and MPEG detection for the AUTO bit does not look at the channel status bits. This
bit is determined by looking for the AC3/MPEG header in the data stream. See the “AC3/MPEG Auto
Detection” section earlier in the data sheet for more details.
3.5 DAC Control Byte (03h)
B7
ZCD
MUT6-MUT1
B6
MUTC
B5
MUT6
B4
MUT5
Mute control bits
0 - Normal output level
1 - Selected DAC output muted
B3
MUT4
B2
MUT3
B1
MUT2
B0
MUT1
MUTC
Controls mute on consecutive zeros function
0 - 512 consecutive zeros will mute DAC
1 - DAC output will not mute on zeros
ZCD
Zero crossing disable
0 - DAC mutes and volume control changes occur on zero-crossings.
1 - DAC mutes and volume control changes occur immediately.
This register defaults to 3Fh.
DS188F4
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