CS4226_04 Datasheet, PDF (21/37 Pages) Cirrus Logic – Surround Sound Codec

CS4226
configuration of the digital filter to maintain the
filter response shown in Figure 9 at multiple
sample rates. The Auxiliary Port Control Byte
selects the de-emphasis control method. De-
emphasis may be enabled under hardware
control, using the DEM pin (DEM2/1/0=4,5,6),
by software control using the DEM bit
(DEM2/1/0=0,1,2,3), or by the emphasis bits in
the channel status data when the S/PDIF re-
ceiver is chosen as the clock source
(DEM2/0/1=7). If no frequency information is
present, the filter defaults to 44.1 kHz.
Gain
dB
0dB
T1=50 µ s
-10dB
T2 = 15 µ s
F1
F2 Frequency
Figure 9. De-emphasis Curve
2.10 HOLD Function
If the digital audio source presents invalid data
to the CS4226, the CS4226 may be configured
to cause the last valid digital input sample to
be held constant. Holding the previous output
sample occurs when the user asserts the
HOLD pin (HOLD=1) at any time during the
stereo sample period, or if a parity, biphase, or
validity error occurs when receiving S/PDIF
data. Parity, biphase, and validity errors can
be independently masked so that no hold oc-
curs. This is done using the VM, PM, and BM
bits in the Input Control Byte. During a HOLD
condition, AUXPort (S/PDIF) input data
is ignored.
DAC outputs can be automatically muted after
an extended HOLD period (>15 samples) by
setting the MOH (Mute On Hold) bit = 0 in the
Auxiliary Port Control Byte. DACs will not be
automatically muted when MOH=1. When the
S/PDIF error condition is removed or the
HOLD pin is de-asserted (HOLD=0), the DAC
outputs will return to one of two different states
controlled by the UMV (Unmute on Valid Data)
bit in the Auxiliary Port Control Byte. When
UMV=0, the DAC outputs will unmute when
the error is removed. When UMV=1, the DACs
must be unmuted in the DAC Control Byte af-
ter the error is removed. This allows the user
to unmute the DAC after the invalid data has
passed through the DSP.
2.11 Power Supply, Layout, and
Grounding
As with any high resolution converter, the
CS4226 requires careful attention to power
supply and grounding arrangements to
optimize performance. Figure 1 shows the
recommended power arrangement with VA
connected to a clean +5V supply. VD should
be derived from VA through a 2 ohm resistor.
VD should not be used to power additional
circuitry. Pins 18, 20, 39 and 41, AGND and
DGND should be connected together at the
CS4226. DGND for the CS4226 should not be
confused with the ground for the digital section
of the system. The CS4226 should be
positioned over the analog ground plane near
the digital/analog ground plane split. The
analog and digital ground planes must be
connected elsewhere in the system. The
CS4226 evaluation board, CDB4226,
demonstrates this layout technique. This
technique minimizes digital noise and insures
proper power supply matching and
sequencing. Decoupling capacitors for VA,
VD, and CMOUT should be located as close to
the device package as possible. See Crystal's
DS188F4
21