CS4226_04 Datasheet, PDF (13/37 Pages) Cirrus Logic – Surround Sound Codec

CS4226
in the digital domain. The change from analog
to digital attenuation occurs at -23 dB. Level
changes only take effect on zero crossings to
minimize audible artifacts. If there is no zero
crossing, then the requested level change will
occur after a time-out period between 512 and
1024 frames (11.6 ms to 23.2 ms at 44.1 kHz
frame rate). There is a separate zero crossing
detector for each channel. Each ACC bit (Ac-
ceptance bit) in the DAC Status Report Byte
gives feedback on when a volume control
change has taken effect. This bit goes high
when a new setting is loaded and returns low
when it has taken effect. Volume control
AOUT
11 kΩ
22 kΩ
3.9 kΩ
1000pF
CMOUT
5 kΩ
150pF
_
+
Example
Op-Amps
are
MC33078
0.47 µ F
2-Pole Butterworth Filter
560 pF
5.85 kΩ
1.1 kΩ 4.75 kΩ
AOUT
1.21 kΩ
_
5600 pF
5600 pF ⁺
CMOUT
5 kΩ
0.47 µ F
3-Pole Butterworth Filter
Figure 3. Butterworth Filter Examples
changes can be instantaneous by setting the
Zero Crossing Disable (ZCD) bit in the DAC
Control Byte to 1.
Each output can be independently muted via
mute control bits, MUT6-1, in the DAC Control
Byte. The mute also takes effect on a zero-
crossing or after a timeout. In addition, the
CS4226 has an optional mute on consecutive
zeros feature, where all DAC outputs will mute
if they receive between 512 and 1024 consec-
utive zeros (or -1 code) on all six channels.
A single non-zero value will unmute the DAC
outputs. This feature can be disabled with the
MUTC bit in the DAC Control Byte. When us-
ing the internal PLL as the clock source, all
DACs will instantly mute when the PLL detects
an error.
2.4 Clock Generation
The master clock to operate the CS4226 may
be generated by using the on-chip inverter and
an external crystal, by using the on-chip PLL,
or by using an external clock source. In all
modes it is required to have SCLK and LRCK
synchronous to the selected master clock.
2.4.1 Clock Source
The CS4226 requires a high frequency master
clock to run the internal logic. The Clock
Source bits, CS0/1/2 in Clock Mode Byte, de-
termine the source of the clock. A high fre-
quency crystal can be connected to XTI and
XTO, or a high frequency clock can be applied
to XTI. In both these cases, the internal PLL is
disabled, and the VCO turns off. The external-
ly supplied high frequency clock can be
256 Fs, 384 Fs or 512 Fs; this is set by the
CI0/1 bits in the Clock Mode Byte. When using
the on-chip crystal oscillator, external loading
capacitors are required, see Figure 1. High fre-
quency crystals (>8 MHz) should be parallel
resonant, fundamental mode and designed for
DS188F4
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