CS4226_04 Datasheet, PDF (20/37 Pages) Cirrus Logic – Surround Sound Codec

CS4226
2.7 Power-up/Reset/Power Down
Mode
Upon power up, the user should hold PDN=0
until the system’s power supply has stabilized.
In this state, the control port is reset to its de-
fault settings. When PDN goes high, the de-
vice remains in a low power mode in which the
control port is active, but CMOUT will not sup-
ply current. The desired settings should be
loaded in while keeping the RS bit set to 1.
Normal operation is achieved by setting the
RS bit to zero in the Converter Control Byte.
Once set to 0, the part powers up and an offset
calibration occurs. This process lasts approxi-
mately 50 ms.
Reset/power down is achieved by lowering the
PDN pin causing the part to enter power down.
Once PDN goes high, the control port is func-
tional and the desired settings should be load-
ed in while keeping the RS bit set to 1. The
remainder of the chip remains in a low power
reset state until the RS bit in the Converter
Control Byte is set to 0.
The CS4226 will also enter a stand-by mode if
the master clock source stops for approxi-
mately 10 µs or if the LRCK is not synchro-
nous to the master clock. The control port will
retain its current settings when in stand-by
mode.
2.8 DAC Calibration
Output offset voltage is minimized by an inter-
nal calibration cycle. A calibration will automat-
ically occur anytime the part comes out of
reset, including the power-up reset, when the
master clock source to the part changes by
changing the CS or CI bits in the Clock Mode
Byte or when the PLL goes out of lock and
then re-locks.
The CS4226 can be re-calibrated whenever
desired. A control bit, CAL, in the Converter
Control Byte, is provided to initiate a calibra-
tion. The sequence is:
1) Set CAL to 1, the CS4226 sets CALP to 1
and begins to calibrate.
2) CALP will go to 0 when the calibration is
completed.
Additional calibrations can be implemented by
setting CAL to 0 and then to 1.
2.9 De-Emphasis
The S/PDIF receiver can be enabled to pro-
cess 24 bits of received data (20 bits of audio
data and four auxiliary bits) or process 20 bits
of audio data (no auxiliary bits). Setting
DEM24=0 in the Auxiliary Port Control Byte,
will enable all 24 received data bits to be pro-
cessed with de-emphasis when de-emphasis
is enabled. When setting DEM24=1, the four
auxiliary bits in the receiver data stream will
pass through unchanged and only the 20 au-
dio data bits will be processed.
The CS4226 is capable of digital de-emphasis
for 32, 44.1, or 48 kHz sample rates. Imple-
mentation of digital de-emphasis requires re-
SDA
00100
ADDR
AD1-0
Note 1
R/W
ACK
DATA
1-8
ACK
DATA
1-8
ACK
SCL
Start
Stop
Note 1: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 8. Control Port Timing, I²C Mode
20
DS188F4