CS4226_04 Datasheet, PDF (14/37 Pages) Cirrus Logic – Surround Sound Codec

CS4226
20 pF loading (equivalent to 40 pF to ground
on each leg).
Alternatively, the on-chip PLL may be used to
generate the required high frequency clock.
The PLL input clock is 1 Fs, and may be input
from LRCKAUX, LRCK, or from XTI/XTO. In
this last case, a 1 Fs clock may be input into
XTI, or a 1 Fs crystal attached across
XTI/XTO. When an external 1 Fs crystal is at-
tached, extra components will be required, see
Figure 1. The PLL will lock onto a new 1 Fs
clock in about 90 ms. If the PLL input clock is
removed, the VCO will drift to the low frequen-
cy end of its frequency range.
The PLL can also be used to lock to an S/PDIF
data source on RX1, RX2, RX3, or RX4.
Source selection is accomplished with the
CS2/1/0 bits in the Clock Mode Byte. The PLL
will lock to an S/PDIF source in about 90 ms.
Finally, the PLL has two filter loop current
modes, normal and high current, that are se-
lected via the LC bit in the Converter Control
Byte. In the normal mode, the loop current is
25 µA. In the high current mode, the loop cur-
rent is 300 µA. The high current mode allows
the use of lower impedance filter components
which minimizes the influences of board con-
tamination. See the table in Figure 1 for filter
component values in each mode.
2.4.2 Master Clock Output
CLKOUT is a master clock output provided to
allow synchronization of external components.
Available CLKOUT frequencies of 1 Fs,
256 Fs, 384 Fs, and 512 Fs, are selectable by
the CO0/1 bits of the Clock Mode Byte.
Generation of CLKOUT for 384 Fs and 512 Fs
is accomplished with an on chip clock multipli-
er and may contain clock jitter. The source of
the 256 Fs CLKOUT is the output of the PLL or
a divided down clock from the XTI/XTO input.
If 384 Fs is chosen as the input clock at XTI
and 256 Fs is chosen as the output, CLKOUT
will have approximately a 33% duty cycle. In all
other cases CLKOUT will typically have a 50%
duty cycle.
2.4.3 Synchronization
The DSP port and Auxiliary port must operate
synchronously to the CS4226 clock source.
The serial port will force a reset of the data
paths in an attempt to resynchronize if non-
synchronous data is input to the CS4226. It is
advisable to mute the DACs when changing
from one clock source to another to avoid the
output of undesirable audio signals as the
CS4226 resynchronizes.
2.5 Digital Interfaces
There are 3 digital audio interface ports: the
audio DSP port, the auxiliary digital audio port,
and the S/PDIF receiver. The serial data is
represented in 2's complement format with the
MSB-first in all formats.
2.5.1 Audio DSP Serial Interface
Signals
The serial interface clock, SCLK, is used for
transmitting and receiving audio data. The ac-
tive edge of SCLK is chosen by setting the
DSCK bit in the DSP Port Mode Byte. SCLK
can be generated by the CS4226 (master
mode) or it can be input from an external SCLK
source (slave mode). Mode selection is set
with the DMS1/0 bits in the DSP Port Mode
Byte. The number of SCLK cycles in one sys-
tem sample period is programmable to be 32,
48, 64, or 128 by setting the DCK1/0 bits in the
DSP Port Mode Byte.
The Left/Right clock (LRCK) is used to indicate
left and right data and the start of a new sam-
ple period. It may be output from the CS4226,
or it may be generated from an external
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