CS4226_04 Datasheet, PDF (7/37 Pages) Cirrus Logic – Surround Sound Codec

CS4226
SWITCHING CHARACTERISTICS (Outputs loaded with 30 pF)
Parameter
Symbol
Audio ADC's & DAC's Sample Rate
Fs
XTI Frequency
(XTI = 256, 384, or 512 Fs)
XTI Pulse Width High
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
XTI Pulse Width Low
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
PLL Clock Recovery Frequency RX, XTI, LRCK, LRCKAUX
XTI Jitter Tolerance
PDN Low Time
(Note 11)
SCLK Falling Edge to SDOUT Output Valid
(DSCK = 0) t_dpd
Min
4
1.024
10
21
31
10
21
31
30
-
500
-
LRCK edge to MSB valid
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
Master Mode
SCLK Period
SCLK Falling to LRCK Edge
SCLK Duty Cycle
Slave Mode
SCLK Period
SCLK High Time
SCLK Low Time
SCLK Rising to LRCK Edge
LRCK Edge to SCLK Rising
t_lrpd
(DSCK=0) t_ds
(DSCK=0) t_dh
t_sck
(DSCK=0) t_mslr
-
-
-
---------1----------
( 256 )F s
-
-
t_sckw
(DSCK=0)
(DSCK=0)
t_sckh
t_sckl
t_lrckd
t_lrcks
---------1----------
( 128 )F s
40
40
20
40
Typ
Max
Units
-
50
kHz
-
26
MHz
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
50
kHz
500
-
ps
-
-
ns
-
---------1---------- + 20 ^ns
( 384 )F s
-
40
ns
-
25
ns
-
25
ns
-
-
ns
±10
-
ns
50
-
%
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
Notes: 11. After powering up the CS4226, PDN should be held low until the power supply is settled.
SCLK*
SCLKAUX*
(output)
LRCK
LRCKAUX
(output)
t _sck
t _mslr
SDOUT1
SDOUT2
Audio Ports Master Mode Timing
LRCK
LRCKAUX
(input)
t _lrckd
t _lrcks
t _sckh
tsckl
SCLK*
SCLKAUX*
(input)
SDIN1
SDIN2
SDIN3
DATAUX
SDOUT1
SDOUT2
t _sckw
t_lrpd tds
tdh
MSB
tdpd
MSB-1
*SCLK, SCLKAUX shown for DSCK = 0 and ASCK = 0.
SCLK & SCLKAUX inverted for DSCK = 1 and ASCK = 1, respectively.
Audio Ports Slave Mode and Data I/O timing
DS188F4
7