CS4226_04 Datasheet, PDF (11/37 Pages) Cirrus Logic – Surround Sound Codec

CS4226
2 FUNCTIONAL DESCRIPTION
2.1 Overview
The CS4226 has 2 channels of 20-bit analog-
to-digital conversion and 6 channels of 20-bit
digital-to-analog conversion. A mono 20-bit
ADC is also provided. All ADCs and DACs are
delta-sigma converters. The stereo ADC in-
puts have adjustable input gain, while the DAC
outputs have adjustable output attenuation.
The device also contains an S/PDIF receiver
capable of receiving compressed AC-3/MPEG
or uncompressed digital audio data.
Digital audio data for the DACs and from the
ADCs is communicated over separate serial
ports. This allows concurrent writing to and
reading from the device. The CS4226 func-
tions are controlled via a serial microcontroller
interface. Figure 1 shows the recommended
connection diagram for the CS4226.
2.2 Analog Inputs
2.2.1 Line Level Inputs
AIN1R, AIN1L, AIN2R, AIN2L, AIN3R, AIN3L
and AINAUX are the line level input pins (See
Figure 1). These pins are internally biased to
the CMOUT voltage. A 10 µF DC blocking ca-
pacitor placed in series with the input pins al-
lows signals centered around 0V to be input to
the CS4226. Figure 2 shows an optional dual
op amp buffer which combines level shifting
with a gain of 0.5 to attenuate the standard line
level of 2 Vrms to 1 Vrms. The CMOUT refer-
ence level is used to bias the op-amps to ap-
proximately one half the supply voltage. With
this input circuit, the 10 µF DC blocking caps in
Figure 1 may be omitted. Any remaining DC
offset will be removed by the internal high-
pass filters.
100 pF
3.3 µ F
Line In
20 k
Right
Example
Op-Amps are
MC34074 or
MC33078
0.47 µ F
10 k
-
+
5k
AINxR
CMOUT
3.3 µ F
Line In
20 k
Left
+
-
10 k
AINxL
100 pF
Figure 2. Optional Line Input Buffer
Selection of stereo the input pair (AIN1L/R,
AIN2L/R or AIN3L/R) for the 20-bit ADC's is
accomplished by setting the AIS1/0 bits (ADC
analog input mux control), which are accessi-
ble in the ADC Control Byte. On-chip anti-
aliasing filters follow the input mux providing
anti-aliasing for all input channels.
The analog inputs may also be configured as
differential inputs. This is enabled by setting
bits AIS1/0=3. In the differential configuration,
the left channel inputs reside on pins 10 and
11, and the right channel inputs reside on pins
12 and 13 as described in Table 2 below. In
differential mode, the full scale input level is
2 Vrms.
Single-ended
AIN3L
AIN3R
AIN2L
AIN2R
AIN1L
AIN1R
Pin #
Pin 10
Pin 9
Pin 11
Pin 12
Pin 14
Pin 13
Differential Inputs
AINL+
unused
AINL-
AINR-
unused
AINR+
Table 2. Single-ended vs. Differential Input Pin
Assignments
DS188F4
11