EP9312 Datasheet, PDF (7/62 Pages) Cirrus Logic – Universal Platform System-on-chip Processor

EP9312
Universal Platform SOC Processor
IDE Interface
The IDE Interface provides an industry-standard
connection to two AT Advanced Packet Interface (ATAPI)
compliant devices. The IDE port will attach to a master
and a slave device. The internal DMA controller performs
all data transfers using the Multiword DMA and Ultra
DMA modes. The interface supports the following
operating modes:
• PIO Modes 0 thru 4
• Ultra DMA Modes 0 thru 3
Table C. IDE Interface Pin Assignments
Pin Mnemonic
Pin Description
DD[15-0]
IDEDA[2-0]
IDECSn[0,1]
DIORn
DIOWn
DMACKn
IDE Data bus
IDE Device address
IDE Chip Select 0 and 1
IDE Read Strobe
IDE Write Strobe
IDE DMA acknowledge
Ethernet Media Access Controller (MAC)
The MAC subsystem is compliant with the ISO/TEC
802.3 topology for a single shared medium with several
stations. Multiple MII-compliant PHYs are supported.
Features include:
• Supports 1/10/100 Mbps transfer rates for home /
small-business / large-business applications
• Interfaces to an off-chip PHY through industry
standard Media Independent Interface (MII)
Table D. Ethernet Media Access Controller Pin Assignments
Pin Mnemonic
Pin Description
MDC
MDIO
RXCLK
MIIRXD[3:0]
RXDVAL
RXERR
TXCLK
MIITXD[3:0]
TXEN
TXERR
CRS
CLD
Management Data Clock
Management Data I/O
Receive Clock
Receive Data
Receive Data Valid
Receive Data Error
Transmit Clock
Transmit Data
Transmit Enable
Transmit Error
Carrier Sense
Collision Detect
Serial Interfaces (SPI, I²S, and AC ’97)
The SPI port can be configured as a master or a slave,
supporting the National Semiconductor^®, Motorola^®, and
Texas Instruments^® signaling protocols.
The AC'97 port supports multiple codecs for multichannel
audio output with a single stereo input. Three I²S ports
can be configured to support six-channel, 24-bit audio.
These ports are multiplexed so that I²S port 0 will take
over either the AC'97 pins or the SPI pins. The second
and third I2S ports' serial input and serial output pins are
multiplexed with EGPIO[4,5,6,13]. The clocks supplied in
the first I2S port are also used for the second and third
I2S ports.
• Normal Mode: One SPI Port and one AC’97 Port
• I²S on SSP Mode: One AC’97 Port and up to three I²S
Ports
• I²S on AC’97 Mode: One SPI Port and up to three I²S
Ports
‘
Table E. Audio Interfaces Pin Assignment
Pin
Name
Normal Mode
I2S on SSP
Mode
Pin
Description
Pin Description
I2S on AC'97
Mode
Pin Description
SCLK1 SPI Bit Clock I2S Serial Clock SPI Bit Clock
SFRM1 SPI Frame Clock I2S Frame Clock SPI Frame Clock
SSPRX1 SPI Serial Input I2S Serial Input SPI Serial Input
SSPTX1
SPI Serial
Output
I2S Serial Output SPI Serial Output
(No I2S Master
Clock)
ARSTn AC'97 Reset AC'97 Reset
I2S Master Clock
ABITCLK AC'97 Bit Clock AC'97 Bit Clock I2S Serial Clock
ASYNC
AC'97 Frame
Clock
AC'97 Frame
Clock
I2S Frame Clock
ASDI
AC'97 Serial
Input
AC'97 Serial Input I2S Serial Input
ASDO
AC'97 Serial
Output
AC'97 Serial
Output
I2S Serial Output
Raster/LCD Interface
The Raster/LCD interface provides data and interface
signals for a variety of display types. It features fully
programmable video interface timing for non-interlaced
flat panel or dual scan displays. Resolutions up to
1024 x 768 are supported from a unified SDRAM based
frame buffer. A 16-bit PWM provides control for LCD
panel contrast.
DS515PP7
©Copyright 2005 Cirrus Logic (All Rights Reserved)
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