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EP9312 Datasheet, PDF (32/62 Pages) Cirrus Logic – Universal Platform System-on-chip Processor
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EP9312
Universal Platform SOC Processor
PIO Data Transfers
Parameter
Cycle time
Address valid to DIORn / DIOWn setup
DIORn / DIOWn 16-bit
DIORn / DIOWn recovery time
DIOWn data setup
DIOWn data hold
DIORn data setup
DIORn data hold
DIORn data high impedance state
DIORn / DIOWn to address valid hold
Read Data Valid to IORDY
active (if IORDY initially low after tA)
IORDY Setup time
IORDY Pulse Width
IORDY assertion to release
DIOWn assert to data valid
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(max)
(min)
(min)
(max)
(max)
(max)
(Note 1, 4)
(Note 4)
(Note 1, 4)
(Note 1, 4)
(Note 4)
(Note 2, 4)
(Note 4)
(Note 4)
(Note 3, 4)
(Note 4)
Symbol
Mode 0
(in ns)
Mode 1
(in ns)
Mode 2
(in ns)
Mode 3
(in ns)
Mode 4
(in ns)
t0
600
383
240
180
120
t1
70
50
30
30
25
t2
165
125
100
80
70
t2i
-
-
-
70
25
t3
60
45
30
30
20
t4
0
0
0
0
0
t5
20
20
20
20
20
t6
0
0
0
0
0
t6z
30
30
30
30
30
t9
20
15
10
10
10
tRD
0
0
0
0
0
tA
tB
tC
tDDV
35
1250
5
10
35
1250
5
10
35
1250
5
10
35
1250
5
10
35
1250
5
10
Note:
1. t0 is the minimum total cycle time, t2 is the minimum DIORn / DIOWn assertion time, and t2i is the minimum DIORn / DIOWn
negation time. A host implementation shall lengthen t2 and/or t2i to ensure that t0 is equal to or greater than the value
reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.
2. This parameter specifies the time from the negation edge of DIORn to the time that the data bus is released by the device.
3. The delay from the activation of DIORn or DIOWn until the state of IORDY is first sampled. If IORDY is inactive then the host
shall wait until IORDY is active before the register transfer cycle is completed. If the device is not driving IORDY negated at
the tA after the activation of DIORn or DIOWn, then t5 shall be met and tRD is not applicable. If the device is driving IORDY
negated at the time tA after the activation of DIORn or DIOWn, then tRD shall be met and t5 is not applicable.
4. Timings based upon software control. See User’s Guide.
5. All IDE timing is based upon HCLK = 100 MHz.
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